A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors

Abstract

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 /spl mu/m BiCMOS technology.