A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

Abstract

A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied. A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels. When supplied with 1.4 V, the circuit achieves signal-to-noise-plus-distortion ratio (SNDR) of 30.74 dB and spurious free dynamic range (SFDR) of 36.91 dB and consumes a power of 66 mW with 500-MHz input and 1-GS/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.57 and 0.81 LSB, respectively. The figure of merit (FoM) is 1.75 pJ/conversionstep. The ADC circuit is prototyped in 0.13-μm CMOS process and occupies a core area of 0.45 mm2.