Abstract
An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.
Highlights
Analog-to-digital converters (ADCs) with above 12-bit resolution and sampling frequency above tens of MHz are widely used in modern communications, instrumentation, and high-quality consumer electronics
This paper presents the realization of a low-voltage 0.13-μm CMOS, 12-bit, 20 MS/s ADC
As input stage respectively, the noise performance of each ADCs can be compared in a way. Because both flip-around digital-to-analog converter (FADAC) and multiplying DAC (MDAC) have decided 1-bit most significant bits (MSBs), and the output residue signal has identical full range and the same remaining resolution bits to be further resolved, the design requirement of the following stages-2 to the end in respective ADC is exactly the same, and the noise of these stages referred to the input of stage-2, which is the output of the input stage, is the same
Summary
Analog-to-digital converters (ADCs) with above 12-bit resolution and sampling frequency above tens of MHz are widely used in modern communications, instrumentation, and high-quality consumer electronics. The significant reduction in the supply voltage and various short-channel effects experienced in these deep-submicron processes create both fundamental and practical design limitations, including lower the achievable amplifier gain, signal voltage swing and enhanced noise level. These limitations lead to a tremendous decrease in the ADC performances, especially if the supply voltage is scaled below 1.2 V [11]. The required SNDR of a high resolution ADC necessitates large-size sampling capacitors at the input stage.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
