A 1.41-pJ/b 56-Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS

Abstract

This letter presents a 56.25-Gb/s analog-mixed signal pulse amplitude modulation (PAM)-4 receiver in 7-nm fin field effect transistor (FinFET) CMOS. The receiver uses an analog front-end (AFE) with extensive programmability and can equalize channels with up to 22.3-dB loss at 14 GHz. AFE settings are optimized using a genetic adaptation algorithm to find the global minima for the bit-error-rate (BER). A PAM-4 clock recovery scheme is proposed that reduces the number of required edge samplers for a PAM-4 bang-bang phase detector without degrading the jitter tolerance of the receiver. Using an AFE as opposed to a decision-feedback equalizer (DFE) along with the proposed clock recovery scheme results in low energy consumption of 1.41 pJ/bit.