A 0.6 V 10 bit 120 kS/s SAR ADC for implantable multichannel neural recording

Abstract

A 10 bit fully-differential SAR ADC with multiple input channels is proposed for neural recording implants. The proposed SAR ADC incorporates both energy-efficient switching scheme and low power supply, leveraging on each other's strength to achieve low power consumption. Designed with 0.18 μm CMOS process, the 10 bit SAR ADC can operate at scalable sampling rate under 0.6 V power supply. Including an optimized analog multiplexer, this proposed ADC consumes 0.5 μW at a sampling rate of 120 kS/s and achieves the ENOB of 9.51, which is equivalent to a figure of merit of 7.03 fJ/Conversion step. The active area of this ADC is 386 μm × 345 μm.