9 - Evaluation of Crystalline Defects in Thin, Strained Silicon-Germanium Epitaxial Layers by Optical Shallow Defect Analyzer

Abstract

Performance of silicon transistors is improved by lateral and vertical scaling and therefore, there is an increasing demand for thin epitaxial silicon or silicon-germanium layers in Ultra Large-Scale Integrated (ULSI) circuit fabrication. The applications of epitaxial layers include the base region of the Hetero-junction Bipolar Transistor (HBT), the channel region of Complementary Metal Oxide Semiconductor (CMOS) transistors, and the elevated source and drain regions of CMOS transistors. HBTs are already fabricated on production lines and many kinds of Large-Scale Integrated (LSI) circuits using silicon-germanium HBTs are commercially available. The silicon-germanium HBT has potential for applications in high-speed telecommunication systems and wireless communication systems. Silicon-germanium epitaxial growth, which is a key process in HBT fabrication, has reached mass-production level, however, a method to evaluate the process quality, especially one for evaluating the crystallinity of the grown layers, has not yet been established. The crystallinity of silicon epitaxial layers is usually evaluated by defect etching or lifetime measurement. These methods can be used to evaluate thick epitaxial layers. In recent applications of epitaxial layers in silicon LSIs, the thickness of the epitaxial layers is below 100 nm. New analytical techniques for evaluating the crystallinity of thin epitaxial layers are needed.