Abstract
An introductory discussion is presented to provide specific context to understand reliability trending as nanoscale dimensions (tens of nm) for advanced complementary metal oxide semiconductor (CMOS) technology become ubiquitous, i.e., not just at the transistor gate. There are three main sections: (1) process solutions being developed for Cu interconnects; (2) improving electromigration (EM) margin of Cu-based interconnects; and (3) microstructure effects on EM reliability. Finally, some discussion beyond the use of the canonical Cu interconnect are discussed.
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