6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS

Abstract

Baud-rate clock and data recovery circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received data only once per UI [1,2]. This reduces the number of front-end comparators and clock distribution networks [1]. However, current baud-rate CDRs require an external reference clock [1,2], adding to the system complexity in pin count and clock generation. While frequency detectors (FDs) allow CDR designs to operate without a reference clock and across a wide capture range [3–5], current FDs are not designed for baud-rate CDRs. As well, current FDs rely on sharp data edges and are not designed for significant ISI caused by channel loss at high data rates [3–5]. This work presents a reference-less baud-rate CDR that operates from 22.5Gb/s to 32Gb/s with channel loss up to −14.8dB at Nyquist. An FD scheme is proposed that automatically controls an adjustable PD to correct any frequency error. This eliminates the need for a separate frequency acquisition loop in the CDR. The CDR, with a CTLE and a 1-tap DFE, is fabricated in 28nm CMOS. The entire receiver consumes 3.2pJ/b at 32Gb/s PRBS-31.