Gb/s CDR circuit for large synchronous networks

Abstract

This paper presents a fully integrated clock and data recovery circuit (CDR) for clock distribution in large synchronous networks. By utilizing of a 2-loop architecture, clock and data recovery loop and clock jitter filtering loop, the CDR has no trade-off between its jitter tolerance and jitter filtering. In the CDR loop, a power-efficient 1/4-rate phase frequency detector is applied to provide inherent data demultiplexing and an operation without an external reference clock. In the clock jitter filtering loop, an integrated low jitter LC-VCO is used to improve the jitter of recovered clock. The CDR was implemented in 0.18 mum CMOS technology. It can provide a clock with jitter of 4.2ps rms from 2Gb/s serial data with ISI jitter 150ps P-P.