Abstract
57-65 GHz differential and transformer-coupled power and variable-gain amplifiers using a commercial 90 nm digital CMOS process are presented. On-chip transformers combine bias, stability and input/interstage matching networks to enable compact designs. Balanced transmission lines with artificial dielectric strips provide substrate shielding and increase the effective dielectric constant up to 54 for further size reduction. Consequently, the designed three-stage power amplifier occupies only an area of only 0.15 mm2. Under a 1.2 V supply, it consumes 70 mA and obtains small-signal gains exceeding 15 dB, saturated output power over 12 dBm and associated peak power-added efficiency (PAE) over 14% across the band. The variable-gain amplifier, based on the same principle, achieved a peak gain of 25 dB with 8 dB of gain variation.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.