Abstract
A 57–65GHz differential and transformer-coupled power amplifier using a commercial 90nm digital CMOS process is presented. On-chip transformers combine bias, stability and input/interstage matching networks for a compact design with an area of 0.15mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The three-stage amplifier consumes 70mA under 1.2V supply voltage. The small-signal gain generally exceeds 15dB with saturated output power levels over 12dBm and associated peak power-added efficiency (PAE) greater than 20% (14% across the band).
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