Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

Hayeon Jeong,Bonghyuk Park,Changkun Park,Huidong Lee,Sunwoo Kong,Seunghyun Jang

doi:10.3390/app112411691

Hayeon Jeong, Bonghyuk Park + Show 4 more

Open Access

https://doi.org/10.3390/app112411691

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Abstract

In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

Highlights

With the adoption of fifth-generation (5G) communication standards, active research has been conducted on millimeter-wave power amplifiers (PAs); the demand for monolithic microwave integrated circuit (MMIC) operating at Ka-band frequency to satisfy the 5G standards is increasing [1,2]
The link-budget calculations in our study show that if a single PA secures a minimum gain of 27 dB, the transceiver IC does not require additional amplifiers, and can be designed to be more marginal
We designed a PA operating between the 26.5–29.5 GHz band using a 65 nm RFCMOS

Summary

Introduction

With the adoption of fifth-generation (5G) communication standards, active research has been conducted on millimeter-wave (mm-Wave) power amplifiers (PAs); the demand for monolithic microwave integrated circuit (MMIC) operating at Ka-band frequency to satisfy the 5G standards is increasing [1,2]. Studies have been underway to configure single-chip transceivers by utilizing high-integrity characteristics of CMOS [3,4,5]. It may not communicate smoothly if the transceiver path lacks gain, which is calculated to determine the appropriate margin when performing link budget analysis. A PA capable of obtaining high gain was designed, and the problem of stability that may occur due to the high gain was solved using a neutralization capacitor To this end, for the first time, we extracted the optimal value of the neutralization capacitor using a differential structure

Design and Optimization of the Power Amplifier

Size Determination of the Unit Ampliffiier Trraannssiissttoorr

Size Determinatio4nμ1a6fn4dm Analysis of the Neutralized Capacitor

Configuration of Matching Network with Transformers

Conclusions