570-ps 13-mW Josephson 1-kbit NDRO RAM

Abstract

Josephson 1-kbit random access memories (RAM's) have been fabricated using Nb multilayer planarization technology with Nb/AlO/sub x//Nb junctions and Mo resistors. The RAM design has been reported previously. The RAM consists of a 32*32-bit nondestructive readout (NDRO) memory cell array and peripheral circuits. The NDRO memory cell consists of a loop storing three flux quanta and two 3-junction interferometer gates. The peripheral circuits consist of decoders with address inverters, drivers, a sense circuit and reset circuits, where resistor-coupled Josephson logic (RCJL) circuits are used as basic circuits. The RAM circuit size is 4.4*4.4 mm/sup 2/, and the memory cell size is 65*65 mu m/sup 2/. About 10000 Nb/AlO/sub x//Nb junctions with 1030-A/cm/sup 2/ critical current density were contained in the RAM. Minimum line and space widths were 3 and 2 mu m, respectively. The Mo resistors had 1.2 approximately 1.3 Omega sheet resistance. About 40 percent of the bits were successfully operated with a +or-18-percent bias margin. A minimum 570-ps access time with 13-mW power dissipation was obtained for the highest peripheral circuit bias conditions. >