56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology

Abstract

A 56 Gbps 2-tap 4-level pulse amplitude modulation closed-loop decision feedback equalizer (DFE) is designed in 28 nm CMOS technology. The first-tap feedback signal directly tapped from the slicer causes uncontrolled overshoot, resulting in over-correction. With insignificant hardware and power consumption, an overshoot compensation scheme is proposed, which generates an opposite overshoot to compensate the original one. Simulation results show the overshoot caused by different process-voltage-temperature conditions during the sampling aperture is reduced by at least 40%. More than 59% improvement is achieved in recovered eye height over its conventional counterpart with ≥ 9 dB channel loss at 14 GHz. In addition, a two-stage slicer is proposed to resolve the critical timing constraints of the first-tap direct feedback path. The receiver occupies an area of 0.19 mm2, and consumes a power of 179 mW, achieving 3.2 pJ/bit energy efficiency.