4H-SiC Device Scaling Development on Repaired Micropipe Substrates

Abstract

A major obstacle to commercial insertion of silicon carbide device technology into power electronics is the presence of hollow-core defects, known as micropipes, in the substrate material. Although considerable progress has been made to reduce the micropipe density to less than 100 per cm, the continuing presence of these defects is widely believed to be a limiting factor in the development of large-area devices. Additionally, the presence of large numbers of closed-core screw dislocations, dislocation defects and other defects contribute to poor scaling of SiC power devices [1]. A process to reduce the micropipe density by filling the defects with silicon carbide and covering the repaired material with a Liquid Phase Epitaxy (LPE) layer has been developed at TDI, Inc. [2-5]. Large area Schottky diode device performance on SiC epi layers grown using Chemical Vapor Deposition (CVD) on both conventional and repaired substrates at the Emerging Materials Research Laboratory (EMRL) have also been reported [6]. One result of these early experiments was a significant improvement in the surface morphology (reduction of step-bunching in the LPE layer) of the reduced micropipe substrate material. More recently, a transmission electron microscopy (TEM) investigation of TDI’s micropipe reduction method with CVD epi has suggested that few dislocations may be generated at the LPE/CVD interface [7].