Abstract
Three-dimensional (3D) stress, process and device simulation is performed for nMOS-FETs with widths from 0.5 µm to 0.1 µm and gate lengths from 100 nm to 45 nm. Stress originates from a cap-liner with 2 GPa tensile stress. Drift-diffusion simulation with the linear piezoresistance model is employed considering either the position-dependence of stress or using a constant stress tensor obtained from averaging the stress in the source-side of the channel over a cuboid extending over the full device width.
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