Abstract
This presentation will provide a comprehensive landscape of the current status of 3D IC including the main trends of utilizing TSV based stacked 3DIC as well as Si interposer based 2.5D IC packages. The differentiation of the market requirements (and cost) that drives technology development and commercialization will be explained and summarized. TSV less 3DIC development options will be discussed. In addition, brief overview of the challenges of ‘transistor level stacking’ will be provided.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
