Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew

Abstract

This paper addresses a bounded skew clock routing problem in 3D stacked IC designs to enable effective trade-offs between power and clock skew. The existing 3D clock tree synthesis (CTS) techniques for power and temperature management solve the clock routing problem in two steps: (step 1) constructing a zero skew clock tree and (step 2) restructuring the clock tree to minimize the increased clock skew caused by temperature variation. Unlike the previous works, this paper provides various solutions for step 1 by relaxing skew bound rather than one (possibly extreme) solution, so that the task of step 2 is more amenable and effective by reduced or controlled power in step 1. To this end, we propose an algorithm, called BSTDME-3D (bounded skew clock tree with deffered merge embedding for 3D ICs), to solve the bounded skew clock tree embedding problem in 3D ICs for a given tree topology. By utilizing the proposed clock tree embedding algorithm, we setup the (un)buffered 3D CTS flow under a (non-)zero skew bound, and study impacts of skew bound on total wirelength and thus clock power consumption. From the extensive experiments, it is shown that the unbuffered CTS with 100ps skew bound reduces 3D clock wirelength by 16% on average for the 4-die stacked 3D ICs. The buffered CTS with 100ps skew bound reduces 3D clock wirelength by 18%, buffer resource by 25%, and thereby clock power consumption by 16% on average for the 4-die stacked 3D ICs.