3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications

Abstract

This brief presents a CMOS-only ultra low power voltage reference of 0.925V which is designed and simulated in TSMC 180nm technology. Current mixing between Self-Biased Self Cascode MOSFET (SBSCM) and Self Cascode MOSFET (SCM) pair is introduced along with stacking of proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltage generators to get second order curvature compensation. Temperature coefficient (TC) of 3.75ppm$/^{\circ}\mathrm{C}$ over a wide temperature range of $- 55^{\circ}\mathrm{C}$ to $140^{\circ}\mathrm{C}$ is achieved. To feed on the power reduction requirement of low power biomedical applications, the entire circuit is designed in sub-threshold region. Therefore, the total power consumption is 27nW @ 1.45V at room temperature $(27^{\circ}\mathrm{C})$. Furthermore, a supply independent current bias aids in realizing high PSRR of -91dB @ 10Hz / -50dB @ 100MHz and line regulation of 0.0779%/V over a supply range 1.45V to 3.6V. Besides, an employed trimming technique attenuates the process spread from ± 3% to ± 0.3%. Moreover, the proposed design occupies an active area of 0.0054mm2 only.