Abstract

The temperature sensor traditionally implemented using parasitic BJT in CMOS process is showing limitations in deep submicron technology node because of process variations. Since vertical PNP transistor in single n-well submicron process is prone to process variations, it impacts the accuracy of temperature sensor. Secondly, low voltage and low power specification of temperature sensor also goes against the choice of BJT as a temperature sensor. Hence, MOSFET based temperature sensors are now becoming popular both for analog and digital variant. The present work gives design methodology of designing proportional to absolute temperature(PTAT) and complementary to absolute temperature(CTAT) circuits using Inversion Coefficient(IC) as a reference point for given specification of temperature coefficient(TC) and temperature range of 223K to 373K. A relation is established between IC and Zero Temperature Coefficient(ZTC) point which becomes the starting step for choosing bias point for diode connected MOS as temperature sensor. The TC for CTAT voltage which remains constant, can be computed analytically using continuous interpolation equation of drain current. The performance of PTAT and CTAT voltage generation circuits can be optimized using IC as design parameter which gives the sizing factor for MOSFETs. The design capability is shown for 180nm technology node with results validated using Predictive Technology Model(PTM) parameters on HSPICE circuit simulator. The analysis of process variation in V T0 , effect of series resistance R S and R D on PTAT and CTAT voltages and total error budget in form of sensitivity is also outlined in this work.

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