3 - Strain engineering

Abstract

Strain engineering is a general strategy applied in MOSFETs to improve carrier mobility and consequently the conductivity through the channel region. This chapter begins with the basic definitions of strain and mismatch parameters. Then the uniaxial and biaxial strain design in MOSFETs and their benefits and drawbacks to increase the channel mobility are presented. On this track, this chapter continues to cover different techniques to induce strain in transistor structure with a focus on embedded Si1−xGex or Si1−yCyin S/D regions, dual-stress liners (DSL), and stress memorization technique (SMT). In this part, more attention is paid to selective epitaxy of SiGe where the pattern dependency behavior may result in strain variation within a chip or from chip to chip because of layout changes over processed wafers. Later, different models to estimate the critical thickness of strained Si1−xGex materials for the global growth are described and the discussions extend to the growth on pattern substrates and nanoscaled transistors. Finally, different characterization tools to quantify strain amount in nanoscaled transistors have been demonstrated.