Abstract
Ir/Ca0.2Sr0.8Bi2Ta2O9 (CSBT)/HfO2/Si ferroelectric-gate field-effect transistors (FeFETs), which were appropriate for low-voltage 3.3 V operations, were developed. The key to the success was the use of N2-dominant gas mixed with a small amount of O2 in a gas flow during the annealing of the FeFETs at 780 °C for CSBT polycrystallization. The Ir gate was newly developed for overcoming the problem of Pt peeling off from the CSBT surface during the novel annealing process. For maximizing the memory windows of the FeFETs, the optimum flow rate of O2 mixed with 1000-sccm-fixed N2 was found to be as low as 0.5 sccm. The novel annealing process suppressed the SiO2 interfacial layer growth to 2.6 nm thickness. The annealing also improved CSBT ferroelectricity. A 109 cycle endurance and a 105 s retention were demonstrated by 3.3 V writing of the FeFETs.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.