Downsizing of Ferroelectric-Gate Field-Effect-Transistors for Ferroelectric-NAND Flash Memory Cells

Abstract

The world's most downsized ferroelectric-gate field effect transistors (FeFETs) with good electrical properties were successfully fabricated, which were developed as memory cells of ferroelectric-NAND (Fe-NAND), the next generation NAND flash memory. 0.54 μm- and 0.26 μm-gate FeFETs were fabricated and characterized. The stacked gate structure of the FeFETs was Pt/SrBi 2 Ta 2 O 9 (SBT)/Hf-Al-O/Si. Cross-sectional SEM images of the FeFET stacked gates showed steep SBT sidewall angles of 85° which indicated good isolation between neighbor cells in 4F 2 cell array. Threshold voltage difference between program-and-erase (P/E) states of the 0.54 μm-gate FeFETs was 0.54 V when 1±6 V and 10 μs P/E pulses were applied. Static memory windows of the 0.26 μm-gate FeFETs were more than 0.9 V when gate voltage was scanned between 1±5 V. We demonstrated good endurance performances up to 10 9 cycles by applying continuous P/E pulses with 5 V amplitude and 20 μs period to the 0.26 μm-gate FeFETs. The FeFETs showed good retention properties which indicated 10 year retention times by their extrapolated lines.