2D Greedy Algorithm for overlap removal for Mixed-Size Placement in VLSI

Abstract

Placement is a crucial step in the physical design of VLSI. At this stage cells/blocks are placed in a chip optimally without overlaps while minimizing their total interconnect wire length. Modern-day placement involves three phases: Global, legal, and detailed placement. Global placement places cells with some initial overlaps within the chip which are removed by legalization and detailed placement afterward. This paper proposes a 2D-overlap removal algorithm that can be used in between global and legalization to pacify the burden of both legalization and detailed placement. The test outcome for the proposed algorithm on random placement improves overlap removal among cells by 22% on an average with respect to the traditional algorithm.