Optimizing Mixed Size & Large Scale Block Placement Using Greedy Approach

Abstract

In very large scale integration (VLSI) of chip, placement is an important stage where cells or blocks are placed within chip optimally minimizing their interconnect wire-length. Analytical placement approach solves the placement problem in three stages; global, legal and detailed placements. Global placement tries to place cells in chip with some overlaps among cells, which are removed at legal and detailed placement stages. In this work a greedy algorithm for overlap removal among cells has been proposed after global placement, so that the tasks rest on legal and detailed placements can be minimized. Subsequently the proposed algorithm can also be used by analytical placers to expedite the legal and detailed placements . Experimental results for proposed algorithm on random instance of placements reduce overlap by 5% in average as compared to the conventional algorithm.