A Detailed Routing-Aware Detailed Placement Technique

Abstract

In this paper we propose a detailed placement algorithm targeting detailed rout ability for designs at or smaller than 22nm. The sheer number and complexity of routing design rules at these feature sizes preclude direct incorporation of detailed routing rules into a placement algorithm. However, using the detail routing information to guide the placement can significantly reduce the overall design time and improve the performance of the circuit. Our proposed detailed routing-aware detailed placement (DrDp) is developed as an add-on to the detailed placement process to improve detailed rout ability in a relatively short runtime. The proposed technique is added to the code obtained from one of the top three teams in the ISPD 2014 detailed routing-driven placement contest and tested on ISPD 2014 benchmark suite. Numerical results show that the proposed technique can improve the detailed routing quality with no significant change in detailed placement score, total wire length or runtime.