28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation

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In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements. A recent alternative approach employs a dynamic amplifier [1] to achieve a more efficient form of settling, stemming from the fact that slewing is more power efficient than exponential settling (Fig. 28.4.1). For example, at 6b accuracy, the setting time of a dynamic amplifier is about a quarter of that of a conventional opamp (non-slewing) with the same bias current. However, the efficiency of the dynamic amplifier is accompanied by a few undesirable features such as ill-defined gain, and PVT and clock jitter sensitivity. In particular, as the voltage gain of a dynamic amplifier relates to the non-constant transconductance, load capacitance and slewing time (g mA , C LA and t A , respectively, in Fig. 28.4.1), it can drift dramatically with PVT variations. One way to compensate for gain instability is to employ continuous background calibration. However, most of these calibrations require some constraints on the statistical property of the input signal and suffer from long convergence time and design complexity. This paper presents a simple analog approach to effectively stabilize the voltage gain over PVT variations.