20-Mb/s GFSK Modulator Based on 3.6-GHz Hybrid PLL With 3-b DCO Nonlinearity Calibration and Independent Delay Mismatch Control

Abstract

A hybrid two-point modulator which mitigates the nonlinearity problem of a digitally controlled oscillator (DCO) and provides a fine delay mismatch calibration is proposed for high data rate applications. A DCO with a separate high-pass modulation path in which only 3 b are used for a capacitor array is designed for flexible gain partition and simple nonlinearity calibration. A nonuniform multilevel quantizer and a finite-impulse response filter are employed to improve modulation quality and reduce quantization noise for high data rate. In the low-pass modulation, a fractional- ${N}$ divider based on a phase rotator and an additional high-frequency $\Delta \Sigma $ modulator enables fine delay time control between two modulation paths. Delay mismatch calibration circuit based on a time-to-digital converter is designed to calculate the optimum delay time automatically. A prototype 3.6-GHz two-point modulator is implemented in 65-nm CMOS. The modulator performs 20-Mb/s GFSK with the error vector magnitude performance of 3.7%, consuming 10.6 mW from a 1-V supply.