Abstract
This paper presents a hybrid two-point modulator for high data rate modulation. The two-point modulator utilizes a phase selection circuit with a high-frequency ΔΣ modulator (DSM) in low-pass modulation to achieve fine resolution for delay mismatch calibration. For high-pass modulation, a separate multi-bit path is designed for a digitally-controlled oscillator (DCO) in addition to the loop control path. A finite impulse response (FIR) filter is introduced in the high-pass modulation path to suppress quantization noise, while offering time-interleaving operation to mitigate the DCO sensitivity for each switching time. The proposed modulator is implemented in 65nm CMOS. Experimental results show that the modulator can achieve 10Mb/s GFSK modulation with the fine time resolution of 138ps.
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