Abstract
A stitched module with embedded semiconductor die has been fabricated using a Heterogeneous System-in-Package (HSIP) technology in order to create a highly dense integrated Multi-Chip Module (MCM) package solution for reliability testing. This technology is based on Fan-out Wafer-level Packaging (FOWLP) technology which consists of a molded core wafer having embedded devices and Through Mold Vias (TMVs), along with buildup circuitry layers on both sides of the molded core wafer. On both sides of the outer layers are Ball Grid Array (BGA) pads which allow these modules to be stacked using conventional solder attach methods. After the buildup layers are produced on the molded wafer, the individual modules are diced out of the wafer. The completed individual HSIP modules are relatively thin packages, which average about 350um. In this work, solder balls are used to stack the HSIP modules. A clam shell test socket has been built to test the initial stack to ensure all the stitched nets are connected and read their calculated initial resistance values. This 2-High stacked HSIP technology can produce a robust 3D package design that can meet aggressive JEDEC testing requirements for military, aerospace and commercial applications, in order to achieve the lowest power consumption, weight and size. A discussion of our 2-High stacked HSIP technology will be presented along with supporting reliability data.
Published Version
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