19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC

Abstract

Today's multicore processors and complex multimedia SoCs incorporate power management techniques such as dynamic frequency scaling (DFS), which dynamically changes operating frequencies, and dynamic core-count scaling (DCCS), which rapidly power cycles the cores between active and idle states. For digital clocking in such SoCs, the PLL needs to support rapid frequency change and fast locking, both without frequency overshoot, so that SoCs can continue operation without interruption during DFS and start operation right after PLL reset is released during DCCS. Moreover, digital clocking PLLs are also required to have a wide frequency range, low period jitter (JP) and low power. Conventional PLLs like [1] use coarse and fine frequency tuning to achieve both low JP, as well as wide frequency range, but may produce frequency overshoots during initial binary frequency search and during DFS, which can span over multiple coarse bands. Furthermore, a conventional proportional-integral (PI) filter [2] suffers from a tradeoff between fast locking and frequency overshoot. These conventional approaches require the SoC to stop using the PLL clock for thousands of clock cycles to mask these frequency overshoots and cause overhead in DFS and DCCS optimization [6]. Another drawback of conventional PLLs [1–4] is the use of a linearly-tuned DCO (fixed frequency steps), which is not well suited for achieving both wide frequency range and constant JP measured in clock unit-interval percentage (%UI). A constant JP (%UI) is optimal for SoC digital clocking, as a constant percentage of the clock period can be allocated for clock-uncertainties during logic synthesis at any frequency. To address these issues, two techniques are proposed in this DPLL architecture: a) a dual-stage phase-acquisition-based loop filter (DALF), which incorporates a first-order loop for phase-acquisition to achieve fast locking without frequency overshoot, and b) a nonlinear DCO (NDCO), which achieves constant JP across wide frequency range. Using these techniques, a digital PLL in 16nm CMOS achieves ±1.25%UI peak-to-peak JP (p−p JP) over a 0.5-to-9.5GHz range with a short lock-time of 1.2µs.