Abstract

A superior figure-of-merit (FoM) 1200 V class 4H-SiC trench MOSFET with p + shielding region partially surrounded by the buried n region is proposed in this paper. The buried n region is introduced to restrain the lateral extension of the depletion layer formed by p + shielding region at the quasi-saturation (QS) state, which leads to a significant improvement of the transfer and forward characteristics. The buried n region expands the current path in the JFET region, decreasing the JFET resistance and improving the maximum transconductance (gfs). Thereby the QS effect of the device with p + shielding region caused by the JFET region gets effectively suppressed. Moreover, the influences of the parameters of the buried n region on the breakdown voltage (BV), the dynamic characteristic and the gate oxide reliability are investigated to determine the optimized device cell structure. Simulation results show that the specific on-resistance (Ron,sp) of the proposed device with the optimized buried n region is decreased by 19.3%, reaching a value of 1.63 mΩ•cm2. The maximum gfs is enhanced by 30%. The FoM1 (FoM1 = BV2/Ron,sp) is utilized to judge the trade-off relationship between the BV and the Ron,sp, which is improved by 20.5%, reaching 1.45 kV2/mΩ•cm2.

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