12 - The next generations

Abstract

This chapter discusses the current scenario of usage of reduced instruction set computer and complex instruction set computer processors and highlights the future of the same. The MC68000 is a superscalar M68000 compatible processor capable of executing two instructions per clock. Its internal architecture is very similar to that of a design with Harvard data and instruction caches feeding multiple execution units. The execution units are heavily pipelined and feature branch folding and separate write back stages—similar to that used in the PowerPC architecture. The key to its operation is in the instruction decoding. The variable size of the instruction and its complicated decoding cause a lot of difficulties for superscalar design. To get around this restriction, the M68000 instructions are taken in from the instruction cache and are internally converted into a fixed-size instruction format. This internal representation is very similar to that used by a superscalar reduced instruction set processors processor. This instruction conversion is combined with a branch folding mechanism and branch address cache to resolve and remove branch instructions before they enter the primary and secondary instruction units. The design can execute either two integer instructions per clock or an integer with a floating point instruction or branch instruction.