Abstract
For the development of new low-voltage, low-power imaging microsystems, we have designed a 10-bit 20-Msample/s ADC. It is a 3-stage sub-ranging architecture and has a rail-to-rail dynamic input. To achieve low-voltage operation and low- power consumption, specific analog blocks such as op-amps and flash ADCs were required. Complementary CMOS comparators with no static consumption were used to build a new low- power 4-bit flash ADC structure with rail-to-rail input range. A new 1.7 volts, 120 dB op-amp structure was designed. To achieve 20 MHz sampling rate, the ADC makes use of time-interleaving, switched capacitor amplifiers, which perform dynamic frequency compensation to optimize speed and offset cancellation to meet resolution requirement. A 20- Msample/s rate has been obtained with supply voltages down to 2.4 volts to 2.4 volts and 60mW power consumption. This ADC has been fabricated and tested and will be integrated on the same chip with color image sensors in a BICMOS process.
Published Version
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