0.11 μm fully-depleted SOI CMOS devices with 26 nm silicon layer fabricated by bulk compatible process

H Komatsu,T Ohno,K Takeshita,H Nakayama,K Matsumoto,K Koyama

doi:10.1109/soic.2001.957966

0.11 μm fully-depleted SOI CMOS devices with 26 nm silicon layer fabricated by bulk compatible process

H Komatsu, T Ohno + Show 4 more

https://doi.org/10.1109/soic.2001.957966

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Publication Date: Oct 1, 2001

#Fully-depleted SOI CMOS #SOI CMOS Devices + Show 8 more

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Abstract

A design for fully-depleted (FD) SOI CMOS devices is proposed. By optimizing halo/extension implantation and a thin CoSi/sub 2/ process, 0.11 /spl mu/m FD devices with a flat roll-off have been fabricated, even with a 26 nm thick Si layer . Using this bulk compatible technology, a good inverter switching speed of 14 ps (at V/sub dd/=1.2 V) has been achieved.

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