C>inf<GS(D)>/inf</C>inf<S(D)G>/inf<Capacitance Phenomenon of 100nm Fully-Depleted SOI CMOS Devices with HfO>inf<2>/inf<High-K Gate Dielectric Considering Vertical and Fringing Displacement Effects

Abstract

This paper reports the C GS(D) /C S(D)G capacitance phenomenon of 100nm fully-depleted (FD) SOI CMOS devices with HfO 2 high-k gate dielectric considering vertical and fringing displacement effect. According to the 2D simulation results, a unique two-step C S(D)G /C GS versus V G curve exists for the device with the 1.5nm HfO 2 gate dielectric due to the vertical and fringing displacement effects.