Abstract
과학기술위성 2호의 탑재 컴퓨터(OBC)의 EM 모델을 개발하고 기능 및 성능평가를 완료하였다. 과학기술위성 2호의 탑재 컴퓨터는 고성능 CPU를 탑재하여 처리 성능을 향상 시켰으며 중앙 집중식 통신구조를 가지도록 설계하여 위성 시스템 내부의 다른 서브 유닛들과 직접 통신하여 위성의 각종 서브장치들을 조정하도록 하였다. 탑재 컴퓨터에 사용되는 통신모듈, 시스템 감시회로, SEU(Single Event Upset)를 극복하기 위한 로직회로 등 각종 제어 회로들을 FPGA 내에 구현함으로써 소형화, 경량화 및 저 전력화를 추구하고 기술 집약화 하도록 하였다. The Engineering Model of STSAT-2 on-board computer(OBC) was developed and tested completely with other sub-systems. The on-board computer of STSAT-2 has a high- performance PowerPC processors and a structure of centralized network communication. In addition, a lot of logics are implemented by Field Programmable Gate Array, such as interrupt controller, watchdog timer and UART. It could make the weight and size of OBC lighter and smaller. Also, the STSAT-2 on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-1.
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