Моделирование блока восстановления тактовой частоты и данных на основе схемы фазовой автоподстройки частоты

Abstract

In many VLSIs, full amplitude CMOS drivers are used for information transfer via unterminated line. What is more, path length decreases carrying capacity of such interconnection in a greater degree than CMOS drivers’ performance. Because transmit channel considerably garbles transferred information, prevailing solution to this problem are clock data recovery blocks the role of which is to retrieve data along with recovering clock signal. In this work, the process of constructing a clock signal and data recovery unit based on a single-loop phase-locked-frequency scheme that does not require a reference periodic signal is considered. The development of its behavioral model was carried out in the Verilog-AMS hardware description language, and the block modeling at the transistor level was carried out in the 90 nm CMOS technology. In this case, the recovery time was 4.8 microseconds, and the «jitter» indicator of clock signal recovery unit was 7.6 ps. The obtained values of developed clock signal and data recovery unit’s output parameters are up to the best foreign analogues.