ZnO TFTs Research Articles

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

Transparent Multi-Level NAND Flash Memory and Circuits Based on ZnO Thin Film Transistor

A simple compatible process is developed to fabricate NAND flash memory and driving logic circuits simultaneously based on atomic layer deposition zinc oxide thin film transistors (ZnO TFTs), in which the active layer and the floating gate layer both are ZnO thin films. The flash memory exhibits excellent memory properties, including large memory window (9.8 V), long retention performance and even multi-level data (2 bits) writing and reading ability. A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${1}\times {4}$ </tex-math></inline-formula> NAND flash array is designed and tested to verify its storage function. A novel modulated enhancement/flash (E/F) inverter is proposed and used on the logic circuits. Finally, a fully transparent flash system with NAND memory cell and driving logic circuits is realized successfully, which has great potential for application of 3D integrated circuits, transparent or flexible electronics.

Multimodal Electrocorticogram Active Electrode Array Based on Zinc Oxide-Thin Film Transistors.

Active electrocorticogram (ECoG) electrodes can amplify weak electrophysiological signals and improve anti-interference ability; however, traditional active electrodes are opaque and cannot realize photoelectric collaborative observation. In this study, an active and fully transparent ECoG array based on zinc oxide thin-film transistors (ZnO TFTs) is developed as a local neural signal amplifier for electrophysiological monitoring. The transparency of the proposed ECoG array is up to 85%, which is superior to that of the previously reported active electrode arrays. Various electrical characterizations have demonstrated its ability to record electrophysiological signals with a higher signal-to-noise ratio of 19.9dB compared to the Au grid (13.2dB). The high transparency of the ZnO-TFT electrode array allows the concurrent collection of high-quality electrophysiological signals (32.2dB) under direct optical stimulation of the optogenetic mice brain. The ECoG array can also work under 7-Tesla magnetic resonance imaging to record local brain signals without affecting brain tissue imaging. As the most transparent active ECoG array to date, it provides a powerful multimodal tool for brain observation, including recording brain activity under synchronized optical modulation and 7-Tesla magnetic resonance imaging.

P‐25: Student Poster: Solution‐Processed CH3NH3PbI3/ZnO Phototransistor with High Photodetectivity

We report a phototransistor using the CH3NH3PbI3/ZnO heterostructure. The CH3NH3PbI3 (MAPbI3) and ZnO are deposited via low‐cost solution process. MAPbI3 coated ZnO TFTs exhibited enhanced photocurrent upon exposure to white light. The heterostructure formed between perovskite and ZnO, works as an efficient electron transport layer. The device had a responsivity of 195 A/W and a high detectivity of 1.10 × 1013 Jones under white light. The high photo‐responsivity and detectivity resulted from the combination of suitable optoelectronic property of MAPbI3 films and the high mobility of the spray coated ZnO films.

Influence of precursor purge time on the performance of ZnO TFTs fabricated by atomic layer deposition

In the present work, the impact of purge time on the performance of TFTs was systematically studied because both ZnO channel layers and Al2O3 insulators were deposited using deionized water (H2O) as oxidant at low temperature. Compared with the Al2O3 thin films (short purge time), the Al2O3 thin films (long purge time) exhibit larger dielectric constant and breakdown voltage. With the increase of purge time, the concentrations of oxygen vacancy and impurities in Al2O3 and ZnO thin films decrease, which is beneficial to improve device stability. A small hysteresis window of 0.39 V and better stability with a minor shift of Vth (0.09 V under positive bias stress) were achieved when the purge time reaches 20 s, which is comparable to the stability achieved by the purge time of 30 s. Besides that, all devices exhibit excellent performance, including a high mobility of 32.5 ± 0.20 cm2V−1s−1, a high Ion/Ioff 108, and an excellent uniformity of electrical characteristics. Therefore, this study not only shows that the stability of oxide TFTs can be enhanced through prolong purge time but also the time cost of the low temperature TFTs can be reduced by setting appropriate purge time.

Influence of Precursor Purge Time on the Performance of Zno Tfts Fabricated by Atomic Layer Deposition

Influence of Precursor Purge Time on the Performance of Zno Tfts Fabricated by Atomic Layer Deposition

Improvement of metal-oxide films by post atmospheric Ar/O2 plasma treatment for thin film transistors with high mobility and excellent stability

Metal-oxide thin-film transistors (MO TFTs) with suitable device performances such as high field-effect mobility (μ FE), low subthreshold swing, high ON/OFF current ratio, and excellent stability under bias stress are of increasing attention for the applications to displays and flexible electronics. Here, we introduce the effect of post atmospheric Ar/O2 plasma (AAP) on spray-pyrolyzed MO film and its role in realizing the high-performance TFT. To better understand the physicochemical mechanism, the spectroscopic, morphologic, and electrical properties of the MO films were studied. From the X-ray photoelectron spectroscope (XPS) results, the composition ratios for Zn:La:O in AAP-treated LaZnO are 4.97:1.00:7.65 before treatment, 5.01:1.00:8.58 upon 5 cycles treatment, and 4.68:1.00:9.72 for 10 cycle treatment. The LaZnO TFT mobilities for 0, 5 and 10 cycles treatment are 8.64, 20.13, and 8.96 cm2 V−1 s−1, respectively. The AAP-treatment on the MO layer could improve the saturation mobility of ZnO, LaZnO, HfZnO, and LiZnO TFTs from 11.65, 8.95, 4.46, and 33.50 cm2 V−1 s−1 to 23.64, 20.13, 12.56, and 48.47 cm2 V−1 s−1, respectively. Furthermore, the optimal TFT shows excellent stability under positive (negative) bias temperature stress (PBTS and NBTS) with a negligible threshold voltage shift.

Performance Optimization of Atomic Layer Deposited ZnO Thin-Film Transistors by Vacuum Annealing

In this letter, high-performance zinc oxide thin-film transistors (ZnO TFTs) have been fabricated on Si substrate by atomic layer deposition (ALD) at 190 °C. The field-effect mobility ( μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> ) can be improved from 18.5 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / V·s to a record high 43.2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / V·s while maintaining a large I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio of 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> after rapid thermal annealing (RTA) under vacuum at 350 °C. The excellent performance can be attributed to the improvement in the ZnO channel and the interface. The oxygen vacancy ratio in ZnO increases from 36.2% to 40.0%. The interface trap density ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) between silicon oxide (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and ZnO decreases from 5.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> to 1.4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . Furthermore, the oxide trap density ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) of the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric reduces from 3.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> to 1.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . Finally, we systematically study the electrical performance of the annealed ZnO device at measurement temperature from room temperature of 20 °C to a much higher temperature of 180 °C without device failure.

Improving the visible-light photoresponse characteristics of a ZnO phototransistor via solution processable Li dopants

Oxygen vacancy states enables Li-doped ZnO TFTs to generate photocurrents through irradiation with visible light.

Room Temperature Hydrogen Sensing Investigation of Zinc Oxide Schottky Thin-Film Transistors: Dependence on Film Thickness

Radio frequency (RF) sputtered ZnO thin-film transistors (ZnO TFTs) with titanium/palladium (Ti/Pd) Schottky source and drain electrodes grown on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /n-Si substrate have been investigated with a compatible fabrication process for different channel thicknesses ranging from 50 to 200 nm as room temperature (RT) hydrogen sensors. Rapid and concentration-dependent (500-4500 ppm) sensor responses (in terms of drain current increase due to the lowering of the Schottky barrier height) with the maximum sensitivity of 72.7% have been achieved excluding the need of heating with relatively fast response/recovery times under RT. Apart from selectivity analysis of the sensors toward methane, acetone, and nitric oxide, structural, optical, mechanical, and electrical characteristics of the devices depending on film thickness are studied. The performance of the sensors in terms of repeatability, time-dependent stability, and under humid ambient conditions has been demonstrated. Hydrogen adsorption kinetics has also been investigated from a thermodynamic analysis.

Sol-gel-derived transparent metal oxide flexible field effect transistors.

ZnO and ZnO:Al thin films have been successfully synthesized by simple solution processable method at low temperature. Highly crystalline (002) preferentially oriented, uniform, and smooth ZnO:Al thin films are produced. The electrical, J-V and C-V, measurements revealed higher current flow and more carrier concentration, respectively, for ZnO:Al samples compared with pristine ZnO. ZnO- and ZnO:Al-based field effect transistors (FETs) were fabricated using SiO2 and TiO2 gate dielectric layers onto flexible plastic, ITO and rigid, p-Si substrates. The ZnO:Al-based FETs measured better transistor performance with both SiO2 and TiO2 gate dielectrics as compared with ZnO-based TFTs. The saturated field effect mobilities 5.78 and 4.96 cm2/Vs were measured for ZnO:Al-based TFTs with SiO2 and TiO2 dielectrics, which reasonably higher than 0.51 and 0.43 cm2/Vs, respectively, measured for pristine ZnO TFTs. The effect of smooth surface and reduced grain boundaries of ZnO:Al layer contributed to measure the low-interface trap density and trap density at grain boundaries. The reported procedure can be applicable to produce large area transparent electronics onto flexible plastic substrates.

P‐122: Mechanical Bending Test of High Mobility ZnO TFTs on PI Substrate by Spray Pyrolysis

We study the effect of mechanical bending on electrical characteristics of flexible ZnO TFTs by spray pyrolysis having μSAT of 11.45 cm2/V.s on PI substrate at 350 °C. The flexible ZnO TFTs exhibit robust electrical characteristics (|ΔVTH |=0.6V) under mechanical‐strain up to 1% and even after repetitive bending for 104 cycles (|ΔVTH |=0.33V).

Gated Hall and field-effect transport characterization of e-mode ZnO TFTs

Two methods of measuring the electronic transport properties of a material are transistor DC-voltage and the Hall effect. Hall mobility measurements of normally off semiconductors can be done by electrostatic doping to lower resistance in the channel. We show that by measuring both, we can compare any value (raw measured as well as calculated data) directly to any other value along an index of FET gate and drain voltage across the entire safe operating area of the device. Our gated Hall technique intrinsic calculations of Hall mobility, typically possible only for bulk or doped materials, for thin-film transistor materials stack up with thickness scaled to practical values.

Effect of annealing of NbLaO dielectric on the electrical properties of ZnO thin-film transistor

ZnO thin-film transistors (ZnO TFTs) with high-k NbLaO as a gate dielectric were fabricated on an indium tin oxide (ITO)-coated glass substrate. The NbLaO film was prepared by the sputtering method at room temperature and then annealed in N2 at 200, 300, and 400 °C. The effect of annealing temperature on the quality of NbLaO and ZnO films, especially on the electrical properties and the bias-stress stability of the ZnO TFT, was investigated. The AFM images reveal that the NbLaO film annealed at 300 °C exhibits a relatively smooth surface morphology with a root mean square roughness of 0.31 nm. AFM and x-ray diffraction measurements confirmed that the grain size of ZnO thin films slightly decreases with the increase of the annealing temperature. Except the mobility of slightly less than that of the device annealed 200 °C, the other electrical properties (off-state current, on/off current ratio, and subthreshold slope) of the ZnO TFT annealed at 300 °C are better than those of the samples annealed at 200 and 400 °C and show excellent gate-bias stress stability, which is due to a combination effect of a smoother interface, a denser structure, and the absence of indium doping in the NbLaO gate dielectric, thus resulting in a lower interfacial trap density.

Impact of Al2O3 deposition temperature on the performance and initial stability of nanocrystalline ZnO thin-film transistors

The initial performance and “time-zero” instability of ZnO TFTs are evaluated using different Al2O3 deposition temperature. Fully-patterned bottom-gate and top-contact devices were fabricated and used as the test structures. The initial TFT performance shows a decrease of saturation mobility from 9.2 to 5.6 cm2/Vˑs; increase in threshold voltage from 2.2 to 2.5 V; and subthreshold swing increase from 115 to 225 mV/DEC, with increasing deposition temperature. The time-zero instability (t = 0 s) shows an increase in threshold voltage shifting of 4.0, 12.8, and 13.6%; a decrease in the subthreshold swing of 5.3%, 17.7%, and 16.3%; and an increase in saturation mobility of 0.8%, 2.8%, and 4.3% with increasing deposition temperature. Results indicate that the primary mechanism of the threshold voltage shifting is the increase in roughness induced interface states due to possible dangling bonds increasing along with the roughness.

P‐15: Gate‐Bias‐Stress‐Induced Instability in Hybrid‐Phase Microstructural ITO‐Stabilized ZnO TFTs

Degradation behaviors of hybrid‐phase microstructural ITO‐stabilized ZnO thin film transistors under gate bias stresses are investigated for the first time. Positive gate bias stresses cause parallel negative shift in characteristics while negative gate bias stresses improve device performance. Incorporated with simulations, the degradation mechanism is tentatively discussed.

High-Performance Flexible ZnO Thin-Film Transistors by Atomic Layer Deposition

Flexible zinc oxide thin film transistors (ZnO TFTs) with a mobility of $ {13}~\text {cm}^{2}/\text {V}\cdot \text {s}$ and an I $_{\text {on}}/\text{I}_{\text {off}}$ ratio of $ {1.5}\times {10}^{8}$ have been fabricated on polyimide substrate, where the ZnO channel is deposited by atomic layer deposition (ALD) at 140 °C. High bending stability has been achieved due to excellent interface quality between alumina (Al2O3) dielectric and ZnO channel with a sharp interface topography. The flexible ZnO device exhibits excellent electrical characteristics even after being bent for 200 000 cycles with a tensile strain of 0.63%. Electrical measurement under a high tensile strain of 2.08% has also been carried out. Moreover, the electrical performance dependence of flexible ZnO TFTs with a tensile strain of 0.78% on temperature from 20 °C to 140 °C has been investigated for the first time.

The effect of Sn on electrical performance of zinc oxide based thin film transistor

In this study, we have effectively fabricated undoped and Sn-doped zinc oxide thin film transistors (ZTO TFTs) with the back-gate structure on commercially purchased p-type Si with a thermally grown SiO2 layer (thickness = 100 nm). The ZTO TFTs were prepared via low-cost solution based spin coating method. We investigated the structural and morphological properties of thin films and the effect of Sn doping on the electrical performance of ZnO TFTs. It has been found that the electrical parameters of the ZnO based transistors have highly affected by Sn doping. The field-effect mobility and on/off ratio of doped TFT increased ~ 40 and 106 times by comparison with undoped TFT, respectively. The best results were obtained from 10% Sn doped ZTO TFT with 3.83 cm2 V−1 s−1 the field effect mobility (µsat), 1 V/dec subthreshold slope (SS), 9 V threshold voltage (Vth), 3 × 108 Ion/Ioff ratio and a high on-current of 1.3 mA.

Short Channel Effect of Solution-Processed ZnO Thin Film Transistors: Optimization for Photolithographic Process

A photolithographic process for the fabrication of short channel solution-processed zinc oxide transistors (ZnO TFTs) was optimized. To avoid damage to the ZnO film by the photolithography, a bottom gate, bottom contact (BG-BC) device structure was adopted. A perhydropolysilazane (PHPS) precursor, thermally annealed and then treated in oxygen plasma, was used as the gate insulator on an aluminum (Al) gate electrode. Al source and drain electrodes, with a minimum channel length of 5 μm were successfully defined using photolithography. A mobility of 1.5×10−2 cm2/Vs, on/off ratio of 106 and good contact between the source and drain (S/D) and semiconductor were achieved for solution-processed ZnO TFTs having various channel lengths, showing no degradation of device properties. The relatively low mobility was attributed to increased roughness of the gate insulator resulting from development during the photolithographic process. These results suggest that short-channel solution-processed ZnO TFTs can be fabricated by adopting optimised photolithographic processes.

Fabrication of Zinc Oxide-Based Thin-Film Transistors by Radio Frequency Sputtering for Ultraviolet Sensing Applications.

In this study, zinc indium tin oxide thin-film transistors (ZITO TFTs) were fabricated by the radio frequency (RF) sputtering deposition method. Adding indium cations to ZnO by co-sputtering allows the development of ZITO TFTs with improved performance. Material characterization revealed that ZITO TFTs have a threshold voltage of 0.9 V, a subthreshold swing of 0.294 V/decade, a field-effect mobility of 5.32 cm2/Vs, and an on-off ratio of 4.7 × 105. Furthermore, an investigation of the photosensitivity of the fabricated devices was conducted by an illumination test. The responsivity of ZITO TFTs was 26 mA/W, with 330-nm illumination and a gate bias of -1 V. The UV-to-visible rejection ratio for ZITO TFTs was 2706. ZITO TFTs were observed to have greater UV light sensitivity than that of ZnO TFTs. We believe that these results suggest a significant step toward achieving high photosensitivity. In addition, the ZITO semiconductor system could be a promising candidate for use in high performance transparent TFTs, as well as further sensing applications.