Zero-voltage Derivative Switching Research Articles

Analysis and Design of the Suboptimum Class-EM/F3 Resonant Inverter

In this paper, the analysis and design method for the suboptimum Class- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{E}_{\mathrm {M}}/\text{F}_{3}$ </tex-math></inline-formula> inverter (i.e., only the zero-voltage switching (ZVS), the zero-voltage-derivative switching (ZVDS), the zero-current switching (ZCS) conditions are satisfied) with a duty ratio D =0.5 are presented. In the proposed design method, a new design parameter K called the slope of switch current (when the switch turns off) is introduced for defining the suboptimum degree and the distance from the optimum condition. By using the design method of the soft switching resonant inverter, the third harmonic filter circuit is innovatively introduced to reduce the current flowing through the parallel capacitor of the main circuit, and greatly reduce the peak switching voltage of the main circuit and auxiliary circuit. And the circuit waveforms and design equations can be derived in detail. Compared with the conventional Class- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{E}_{\mathrm {M}}$ </tex-math></inline-formula> inverter, the proposed inverter can offer the much lower peak switching voltage and higher efficiency. To verify the validity of the proposed method, a Class- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{E}_{\mathrm {M}}/\text{F}_{3}$ </tex-math></inline-formula> inverter operating at 1MHz is designed using the IRFZ24N transistor. The experimental results show that the output power of the new inverter is 15.138W, the efficiency reaches 96.4%, and the peak switching voltage of the main circuit and auxiliary circuit is reduced by 29.3% and 15.6%, respectively. The PSpice-simulation results and the experimental measurement results of the designed inverter are agreed with the analytical results, which verified the effectiveness of the proposed design method.

Load-Independent Class E2 Parallel Resonant DC–DC Converter

This brief presents load-independent Class E2 parallel resonant dc-dc converter, which consists of load-independent Class E parallel resonant inverter and load-independent synchronous Class E voltage-driven low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$dv/dt$ </tex-math></inline-formula> resonant rectifier. The proposed converter achieves zero-voltage-switching (ZVS) and zero-voltage-derivative-switching (ZVDS) at a rated load resistance, and maintains ZVS and a constant dc output voltage over a wide range of load resistance without additional elements or feedback control. The validity of the operation was confirmed by circuit simulation using LTspice and circuit experiments.

Voltage-Source Parallel Resonant Class E Inverter

This paper proposes a voltage-source parallel resonant Class E inverter. The proposed circuit has a shunt capacitor including parasitic capacitance of a switching device and achieves zero-voltage switching and zero-voltage derivative switching at turning- on like a classical Class E inverter. Therefore, high power conversion efficiency is achieved under high operating frequency. Unlike the other Class E inverters, the proposed circuit has no choke inductor or dc blocking capacitor. Moreover, it has a parallel resonant tank unlike the classical Class E inverter. Thus, a circuit protection is not required in a wireless power transfer system. Circuit analysis, circuit simulations, and circuit experiments were carried out. The experimental circuit performed the desired operation and the power conversion efficiency was 93.2% with the output power 4.76 W at the operating frequency 1 MHz.

Generalized Class-E Power Amplifier With Shunt Capacitance and Shunt Filter

This paper presents a generalized analysis of the Class-E power amplifier (PA) with a shunt capacitance and a shunt filter, leading to a revelation of a unique design flexibility that can be exploited either to extend the maximum operating frequency of the PA or to allow the use of larger active devices with higher power handling capability. The proposed PA fulfills zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) conditions, resulting in a theoretical dc-to-RF efficiency of 100%. Explicit design equations for the load-network parameters are derived, and the analytical results are confirmed by harmonic-balance simulations. Two PA prototypes were constructed with one designed at low frequency and the other at high frequency. The first PA, which employs a MOSFET and a lumped-element load-network, delivered a peak drain efficiency $(\!D\!E)$ of 93.3% and a peak output power of 37 dBm at 1 MHz. The second PA, which employs a GaN HEMT and a transmission-line (TL) load-network to provide the drain of the transistor with the required load impedances at the fundamental frequency as well as even and odd harmonic frequencies, delivered a peak $D\!E$ of 90.2% and a peak output power of 39.8 dBm at 1.37 GHz.

Class-DEM Tuned Power Amplifier

This paper proposes a Class-DEM tuned power amplifier. The proposed amplifier achieves zero-voltage switching (ZVS), zero-voltage derivative switching (ZVDS), and zero-current switching (ZCS) at turning- on , and ZVS, ZVDS, ZCS, and zero-current derivative switching at turning- off . Therefore, the switching losses are extremely low, which is suitable for high-frequency operation. Moreover, the switch voltage stress is low, which is no more than its input voltage. A proposed amplifier was designed, built, and tested. The measured power conversion efficiency was 93.2% under the condition of the main input voltage of 46.8 V, the operating frequency of 1 MHz, and the output power of 4.87 W.

Class E/F$_3$ Tuned Power Oscillator

This paper proposes a Class E/F $_3$ tuned power oscillator based on the Class E/F $_3$ amplifier. The oscillator has a feedback-loop circuit and starts the oscillation in automatic. In addition, the oscillator achieves zero-voltage switching and zero-voltage derivative switching; therefore, the switching losses are reduced under high oscillation frequency. Moreover, the third harmonic tuned by providing a third harmonic series resonant circuit reduces the switch voltage stress of the mosfet sufficiently. The oscillator was designed, built and tested using an IRFR120Z power mosfet . Under the condition of the input voltage 6.003 V, following results were shown: the measured oscillation frequency was 801.6 kHz, the output power was 0.9075 W, and the power conversion efficiency was 86.24%.

Class E Power Amplifier Design and Optimization for the Capacitive Coupled Wireless Power Transfer System in Biomedical Implants

The capacitive coupled wireless power transfer (CCWPT) operating at megahertz (MHz) frequency is broadly considered as the promising solution for low power biomedical implants. The class E power amplifier is attractive in MHz range wireless power transfer (WPT) applications due to zero voltage switching (ZVS) and zero voltage derivative switching (ZVDS) properties. The existing design of class E amplifier is investigated only for inductive resonant coupled (IRC) WPT systems; the modelling and optimization of the class E amplifier for CCWPT systems are not deliberated with load variation. Meanwhile, the variations in the coupling distance and load are common in real time applications, which could reduce the power amplifier (PA) efficiency. The purpose of this paper is to model and optimize the class E amplifier for CCWPT systems used in MHz range applications. The analytical model of PA parameters and efficiency are derived to determine the optimal operating conditions. Also, an inductive-capacitive-inductive (LCL) impedance matching network is designed for the robust operation of the PA, which improves the efficiency and maintains required impedance compression. The maximum efficiency of the proposed design reached up to 96.34% at 13.56 MHz and the experimental results are closely matched with the simulation.

An Overview of Resonant Circuits for Wireless Power Transfer

With ever-increasing concerns for the safety and convenience of the power supply, there is a fast growing interest in wireless power transfer (WPT) for industrial devices, consumer electronics, and electric vehicles (EVs). As the resonant circuit is one of the cores of both the near-field and far-field WPT systems, it is a pressing need for researchers to develop a high-efficiency high-frequency resonant circuit, especially for the mid-range near-field WPT system. In this paper, an overview of resonant circuits for the near-field WPT system is presented, with emphasis on the non-resonant converters with a resonant tank and resonant inverters with a resonant tank as well as compensation networks and selective resonant circuits. Moreover, some key issues including the zero-voltage switching, zero-voltage derivative switching and total harmonic distortion are addressed. With the increasing usage of wireless charging for EVs, bidirectional resonant inverters for WPT based vehicle-to-grid systems are elaborated.

A Reduced Switch Voltage Stress Class E Power Amplifier Using Harmonic Control Network

In this paper, a harmonic control network (HCN) is presented to reduce the voltage stress (maximum MOSFET voltage) of the class E power amplifier (PA). Effects of the HCN on the amplifier specifications are investigated. The results show that the proposed HCN affects several specifications of the amplifier, such as drain voltage, switch current, output power capability (Cp factor), and drain impedance. The output power capability of the presented amplifier is also improved, compared with the conventional class E structure. High-voltage stress limits the design specifications of the desired amplifier. Therefore, several limitations can be removed with the reduced switch voltage. According to the results, the maximum drain voltage for the presented amplifier is reduced and subsequently, the output power capability is increased about 25% using the presented structure. Zero-voltage switching condition (ZVS) and zero-voltage derivative switching condition (ZVDS) are assumed in the design procedure. These two conditions are essential for high efficiency achievement in various classes of switching amplifiers. A class E PA with operating frequency of 1 MHz is designed and simulated using advanced design system (ADS) and PSpice software. The theory and simulated results are in good agreement.

Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier

An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier&apos;s performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power‐output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.