Zero Suppression Research Articles

A Monitoring System Based on NB-IoT and BDS/GPS Dual-Mode Positioning

Monitoring system is widely used to detect the environment parameters such as temperature, humidity and position information in cold chain logistic, modern agriculture, hospital and so on. Poor position precision, high communication cost, high packet loss rate are the main problems in current monitoring system. To solve these problems, the paper presents a new monitoring system based on Narrow Band Internet of Things (NB-IoT) and BeiDou system/Global System Position (BDS/GPS) dual-mode positioning. Considering the position precision, a dual-mode positioning circuit based on at6558 is designed, and the calculation formula of the positioning information of the monitored target has been derived. Subsequently, a communication network based on wh-nb75-ba NB-IoT module is designed after compared with the LoRa technology. According to the characteristics of high time correlation of sensor data, an adaptive optimal zero suppression (AOZS) compression algorithm is proposed to improve the efficiency of data transmission. Experiments prove the feasibility and effectiveness of the system from the aspects of measurement accuracy, positioning accuracy and communication performance. The temperature and humidity error are less than 1 °C and 5% RH respectively with the selected sensor chips. The position error is decided by several factors, including the number of satellites used for positioning, the monitored target moving speed and NB-IoT module lifetime period. When the monitored target is stationary, the positioning error is about 2 m, which is less than that of the single GPS or BDS mode. When the monitored target moves, the position error will increase. But the error is still less than that of the single GPS or BDS mode. Then the AOZS compression algorithm is used in actually experiment. The compression ratio (CR) of it is about 10% when the data amount increasing. In addition, the packet loss rate test experiment proves the high reliability of the proposed system.

The SALT-Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment.

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

Fast inference using FPGAs for DUNE data reconstruction

The Deep Underground Neutrino Experiment (DUNE) will be a world-class neutrino observatory and nucleon decay detector aiming to address some of the most fundamental questions in particle physics. With a modular liquid argon time-projection chamber (LArTPC) of 40 kt fiducial mass, the DUNE far detector will be able to reconstruct neutrino interactions with an unprecedented resolution. With no triggering and no zero suppression or compression, the total raw data volume would be of order 145 EB/year. Consequently, fast and affordable reconstruction methods are needed. Several state-of-theart methods are focused on machine learning (ML) approaches to identify the signal within the raw data or to classify the neutrino interaction during the reconstruction. One of the main advantages of using those techniques is that they will reduce the computational cost and time compared to classical strategies. Our plan aims to go a bit further and test the implementation of those techniques on an accelerator board. In this work, we present the accelerator board used, a commercial off-the-shelf (COTS) hardware for fast deep learning (DL) inference based on an FPGA, and the experimental results obtained outperforming more traditional processing units. The FPGA-based approach is planned to be eventually used for online reconstruction.

A real time sorting algorithm to time sort any deterministic time disordered data stream

In new generation high intensity high energy physics experiments, millions of free streaming high rate data sources are to be readout. Free streaming data with associated time-stamp can only be controlled by thresholds as there is no trigger information available for the readout. Therefore, these readouts are prone to collect large amount of noise and unwanted data. For this reason, these experiments can have output data rate of several orders of magnitude higher than the useful signal data rate. It is therefore necessary to perform online processing of the data to extract useful information from the full data set. Without trigger information, pre-processing on the free streaming data can only be done with time based correlation among the data set. Multiple data sources have different path delays and bandwidth utilizations and therefore the unsorted merged data requires significant computational efforts for real time manifestation of sorting before analysis. Present work reports a new high speed scalable data stream sorting algorithm with its architectural design, verified through Field programmable Gate Array (FPGA) based hardware simulation. Realistic time based simulated data likely to be collected in an high energy physics experiment have been used to study the performance of the algorithm. The proposed algorithm uses parallel read-write blocks with added memory management and zero suppression features to make it efficient for high rate data-streams. This algorithm is best suited for online data streams with deterministic time disorder/unsorting on FPGA like hardware.

ARTROC—a readout ASIC for GEM-based full-field XRF imaging system

In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called ARTROC, being part of a full-field X-ray fluorescence spectroscopy (XRF) imaging system equipped with a standard three stage Gas Electron Multiplier (GEM) detector of 10×10 cm2 area. The ARTROC consists of 64 independent channels, allowing for simultaneous recording of the amplitudes (energy sub-channel) and time stamps (timing sub-channel) of incoming signals. Thanks to the implemented token-based read out of derandomizing buffers, the ASIC also provides data sparsification and full zero suppression. Reconstruction of the hit positions is performed in an external data acquisition system by matching the time stamps of signals recorded in X- and Y-strips. The amplitude information is used for centre of gravity finding in clusters of signals on neighbouring strips belonging to the same detection events. The ASIC could work in one of six gain modes and one of two speed modes. In a slower mode the maximum count rate per channel is 105/s while in a faster mode it is three times higher. The ARTROC comprises also input protection circuits against possible random discharges inside active detector volume, so it can be used without any additional input components. The ASIC has been designed in 350 nm CMOS process. The basic functionality and parameters have been evaluated using the testability functions implemented in the ASIC design. The ASIC has been also tested in a fully equipped GEM detector set-up with X-rays source.

Development and commissioning of the HARDROC based readout for the INO-ICAL experiment

Glass based Resistive Plate Chambers (RPCs) are going to be used as an active element in the Iron Calorimeter (ICAL) experiment at the India based Neutrino Observatory (INO), which is being constructed to study atmospheric neutrinos. Though the RPC detector operational parameters are more or less finalized, the readout electronics is being developed using various technologies. The ICAL experiment will consist of about 29,000 RPC detectors of 2 m × 2 m in size with each detector having 64 readout channels both in the X and Y directions. The present study focusses on multi-channel electronics based on SiGe 350 nm technology as an option for the INO-ICAL RPC detectors. The study includes commissioning and usage of frontend application specific integrated circuit (ASIC) HARDROC chip in which 64 channels are handled independently to perform zero suppression. We present first testbench results using the HARDROC chip with the aim to use it finally in the ICAL experiment.

Readout system of TPC/MPD NICA project

The time-projection chamber (TPC) is the main tracking detector in the MPD/NICA. The information on charge-particle tracks in the TPC is registered by the MWPG with cathode pad readout. The frontend electronics (FEE) are developed with use of modern technologies such as application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), and data transfer to a concentrator via a fast optical interface. The main parameters of the FEE are as follows: total number of channels, ~95 000; data stream from the whole TPC, 5 GB/s; low power consumption, less than 100 mW/ch; signal to noise ratio (S/N), 30; equivalent noise charge (ENC), <1000e– (Cin = 10–20 pF); and zero suppression (pad signal rejection ~90%). The article presents the status of the readout chamber construction and the data acquisition system. The results of testing FEE prototypes are presented.

Zero suppression logic of the ALICE muon forward tracker pixel chipprototype PIXAM and associated readout electronics development

In the framework of the ALICE experiment upgrade at HL-LHC, a new forward tracking detector, the Muon Forward Tracker (MFT), is foreseen to overcome the intrinsic limitations of the present Muon Spectrometer and will perform new measurements of general interest for the whole ALICE physics. To fulfill the new detector requirements, CMOS Monolithic Active Pixel Sensors (MAPS) provide an attractive trade-off between readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This technology has been chosen to equip the Muon Forward Tracker and also the vertex detector: the Inner Tracking System (ITS). Since few years, an intensive R&D program has been performed on the design of MAPS in the 0.18 μ m CMOS Image Sensor (CIS) process. In order to avoid pile up effects in the experiment, the classical rolling shutter readout system of MAPS has been improved to overcome the readout speed limitation. A zero suppression algorithm, based on a 3 by 3 cluster finding (position and data), has been chosen for the MFT. This algorithm allows adequate data compression for the sensor. This paper presents the large size prototype PIXAM, which represents 1/3 of the final chip, and will focus specially on the zero suppression block architecture. This chip is designed and under fabrication in the 0.18 μ m CIS process. Finally, the readout electronics principle to send out the compressed data flow is also presented taking into account the cluster occupancy per MFT plane for a single central Pb-Pb collision.

The MAPS based PXL vertex detector for the STAR experiment

The Heavy Flavor Tracker (HFT) was installed in the STAR experiment for the 2014 heavy ion run of RHIC. Designed to improve the vertex resolution and extend the measurement capabilities in the heavy flavor domain, the HFT is composed of three different silicon detectors based on CMOS monolithic active pixels (MAPS), pads and strips respectively, arranged in four concentric cylinders close to the STAR interaction point.The two innermost HFT layers are placed at a radius of 2.7 and 8 cm from the beam line, respectively, and accommodate 400 ultra-thin (50 μ m) high resolution MAPS sensors arranged in 10-sensor ladders to cover a total silicon area of 0.16 m2. Each sensor includes a pixel array of 928 rows and 960 columns with a 20.7 μ m pixel pitch, providing a sensitive area of ∼ 3.8 cm2. The architecture is based on a column parallel readout with amplification and correlated double sampling inside each pixel. Each column is terminated with a high precision discriminator, is read out in a rolling shutter mode and the output is processed through an integrated zero suppression logic. The results are stored in two SRAM with ping-pong arrangement for a continuous readout. The sensor features 185.6 μ s readout time and 170 mW/cm2 power dissipation. The detector is air-cooled, allowing a global material budget as low as 0.39% on the inner layer. A novel mechanical approach to detector insertion enables effective installation and integration of the pixel layers within an 8 hour shift during the on-going STAR run.In addition to a detailed description of the detector characteristics, the experience of the first months of data taking will be presented in this paper, with a particular focus on sensor threshold calibration, latch-up protection procedures and general system operations aimed at stabilizing the running conditions. Issues faced during the 2014 run will be discussed together with the implemented solutions. A preliminary analysis of the detector performance meeting the design requirements will be reported.

Implementation of High Performance Electronic Circuits for Zero Suppression and Encoding of Digital Signals

This paper presents a design of a data processing circuit for receiving digital signals from front end-electronic board chips of a specific nuclear detector, encoding and triggering them via specific optical links operating at a specific frequency. Such processed signals are then fed to a data acquisition system (DAQ) for analysis. Very high-speed integrated circuit hardware description language (VHDL) algorithms and codes were created to implement this design using field programmable gate array (FPGA) devices. The obtained data were simulated using international standard simulators.

Super-Altro 16: A Front-End System on Chip for DSP Based Readout of Gaseous Detectors

This paper presents the architecture, design and test results of an ASIC specifically designed for the readout of gaseous detectors. The primary application is the readout of the Linear Collider Time Projection Chamber. The small area available (4 mm2 /channel) requires an innovative design, where sensitive analog components and massive digital functionalities are integrated on the same chip. Moreover, shut down (power pulsing) features are necessary in order to reduce the power consumption. The Super-Altro is a 16-channel demonstrator ASIC involving analog and digital signal processing. Each channel contains a low noise Pre-Amplifier and Shaping Amplifier (PASA), a pipeline ADC, and a Digital Signal Processor (DSP). The PASA is programmable in terms of gain and shaping time and can operate with both positive and negative polarities of input charge. The 10-bit ADC samples the output of the PASA at a frequency up to 40 MHz before providing the digitized signal to the DSP which performs baseline subtraction, signal conditioning, drift correction and zero suppression. The chip has been fabricated in a 130 nm CMOS technology. Test measurements show correct functionality of the full system, and demonstrate that, using appropriate design techniques, the extensive digital circuitries produce little or no degradation of analog performance (particularly noise).

A reticle size CMOS pixel sensor dedicated to the STAR HFT

ULTIMATE is a reticle size CMOS Pixel Sensor (CPS) designed to meet the requirements of the STAR pixel detector (PXL). It includes a pixel array of 928 rows and 960 columns with a 20.7 μm pixel pitch, providing a sensitive area of ∼ 3.8 cm2. Based on the sensor designed for the EUDET beam telescope, the device is a binary output sensor with integrated zero suppression circuitry featuring a 320 Mbps data throughput capability. It was fabricated in a 0.35 μm OPTO process early in 2011. The design and preliminary test results, including charged particle detection performances measured at the CERN-SPS, are presented.

Online Digital Data Processing for the T2K Fine Grained Detector

The T2K Fine Grained Detector (FGD) is an active neutrino target that uses segmented scintillator bars to observe short-range particle tracks. 8448 multipixel photon counters (MPPCs) coupled to wavelength shifting fibres detect scintillator light. An application specific integrated circuit (ASIC) shapes the MPPC waveform and uses a switched capacitor array (SCA) to store up to 511 analog samples over 10.22 μs. High and low attenuation channels for each MPPC improve dynamic range. 12-bit serial quad-ADCs digitize ASIC analog output and interface with a field programmable gate array (FPGA). Each FPGA simultaneously reads out four ADCs and saves the synchronized samples in an external digital memory. The system produces 13.5 MB of uncompressed data with a target trigger rate of 20 Hz, and requires zero suppression to reduce data size and readout time. Firmware based data compression uses an online pulse-finder that decides whether to output pulse height information, a section of waveform, or to suppress all data. The front end FPGA transfers formatted data to data concentrator cards (DCCs) through a 2 Gb/s optical fiber interface using an efficient custom protocol. We have evaluated the performance of the FGD electronics system and the quality of its online data compression through the course of a physics data run. The average size of a compressed data acquisition is measured as 44 ~ kB.

A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will be changed; hit data from every collision will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that the data rate off chip is minimized. A C++ model has been created for simulation of functionality and data loss, and for system development. A VHDL implementation has been derived from this model.

First reticule size MAPS with digital output and integrated zero suppression for the EUDET-JRA1 beam telescope

A high resolution beam telescope, based on CMOS monolithic active pixel sensors (MAPS), is being developed within the EUDET collaboration. Mimosa26 is the first pixel sensor covering an active area of ∼224mm2 with integrated zero suppression for this telescope. A single point resolution better than 4μm is expected with a pixel pitch of 18.4μm. The matrix is organised in 576 rows and 1152 columns. At the bottom of the pixel array, each column is connected to an offset compensated discriminator to perform the analogue to digital conversion. Digital data are then treated by a zero suppression circuit in order to send useful information. This architecture allows a fast readout frequency of ∼10kframes/s. The paper concentrates on the details of the chip design and its main performances.

Charge collection in the Silicon Drift Detectors of the ALICE experiment

A detailed study of charge collection efficiency has been performed on the Silicon Drift Detectors (SDD) of the ALICE experiment. Three different methods to study the collected charge as a function of the drift time have been implemented. The first approach consists in measuring the charge at different injection distances moving an infrared laser by means of micrometric step motors. The second method is based on the measurement of the charge injected by the laser at fixed drift distance and varying the drift field, thus changing the drift time. In the last method, the measurement of the charge deposited by atmospheric muons is used to study the charge collection efficiency as a function of the drift time. The three methods gave consistent results and indicated that no charge loss during the drift is observed for the sensor types used in 99% of the SDD modules mounted on the ALICE Inner Tracking System. The atmospheric muons have also been used to test the effect of the zero-suppression applied to reduce the data size by erasing the counts in cells not passing the thresholds for noise removal. As expected, the zero suppression introduces a dependence of the reconstructed charge as a function of drift time because it cuts the signal in the tails of the electron clouds enlarged by diffusion effects. These measurements allowed also to validate the correction for this effect extracted from detailed Monte Carlo simulations of the detector response and applied in the offline data reconstruction.

The ALICE silicon pixel detector readout electronics

The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the ALICE inner tracking system (ALICE Collaboration, 1999) [1]. The SPD is built with 120 detector modules (half-staves) and contains about 10 million pixels in total. The half-staves are connected to the off-detector electronics, housed in a control room 100 m away, via bidirectional optical links. The stream of data from the front-end electronics is processed in 20 VME readout modules, called routers, based on FPGAs. Three 2-channel link-receiver daughter cards, also based on FPGAs, are plugged in each router. Each link-receiver card receives data via the optical link from two half-staves, applies the zero suppression and passes them to the router to be processed and sent to the ALICE–DAQ system through the detector data link (DDL). The SPD control, configuration and data monitoring are performed using the VME interface embedded in the router.

CMOS pixel sensor development: a fast read-out architecture with integrated zero suppression

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, which imposes sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. The design architecture, combining pixel array, column-level discriminators and zero suppression circuits, will be presented. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.

Implementation of on-line data reduction algorithms in the CMS Endcap Preshower Data Concentrator Cards

The CMS Endcap Preshower (ES) sub-detector comprises 4288 silicon sensors, each containing 32 strips. The data are transferred from the detector to the counting room via 1208 optical fibres running at 800Mbps. Each fibre carries data from two, three or four sensors. For the readout of the Preshower, a VME-based system, the Endcap Preshower Data Concentrator Card (ES-DCC), is currently under development. The main objective of each readout board is to acquire on-detector data from up to 36 optical links, perform on-line data reduction via zero suppression and pass the concentrated data to the CMS event builder. This document presents the conceptual design of the Reduction Algorithms as well as their implementation in the ES-DCC FPGAs. These algorithms, as implemented in the ES-DCC, result in a data-reduction factor of 20.

Design and performance of the CMS pixel detector readout chip

The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.