As the world collects more data, the electronics industry is demanding faster and more energy efficient supercomputers, but this is becoming an increasingly challenging goal as Moore's law nears its end. Superconducting electronics, and single flux quantum (SFQ) in particular, is a promising option for future exascale supercomputing. Nevertheless, timing uncertainty-represented by the inaccuracy of gates delays-renders the design of high-frequency clock distribution networks (CDN) to be one of the challenges that is impeding SFQ processors from attaining their full promised potential. As a radical solution to this challenge, the hierarchical chains of homogeneous clover-leaves clocking, (HC) 2 LC, was proposed. (HC) 2 LC uses an asynchronous CDN to provide the timing of a fully synchronous system, promising superior robustness over the conventional zero-skew clock trees with modest area and performance overheads. In this article, we propose algorithms that optimize the construction of the (HC) 2 LC network. We optimize both the insertion delay and the gates-assignment problem resulting in area reduction of 51%, and yield improvement of 166% compared to the unoptimized (HC) 2 LC. Moreover, we propose a placement-aware variation model, and we present a tool, the qHC 2 LC, using both of which, we perform a complete comparison between zero-skew clock trees and (HC) 2 LC. Our simulations show that averaging over the ISCAS'85 benchmark circuits, at the same speed, and with an area overhead of 9%, (HC) 2 LC achieves 52% and 211% yield improvement over zero-skew trees at low and medium ranges of σ of gate delays, respectively.