Zero-sequence Circulating Current Research Articles

Optimal Vector Sequences for Simultaneous Reduction of the Switching Loss, Zero-Sequence Circulating Current, and Torque Ripple in Two Parallel Interleaved Inverter-Fed PMSM Drives

The two-parallel interleaved converters system is essentially a multilevel converter and introduces more vector redundancies than a single converter, leaving a large space for vector sequences optimization for the simultaneous optimization of crucial indicators. However, the vector redundancies have not been fully explored by previous studies to achieve multiple crucial indicators optimization. This article aims to obtain high efficiency and low torque ripples for the two-parallel interleaved converters-fed permanent-magnet synchronous motor (PMSM), which are dominantly affected by the switching loss, zero-sequence circulating current (ZSCC), and torque ripples. First, given the vector redundancies, this article explores the available vector sequences according to switching times, the minimal torque ripple, and ZSCC with a priority of the switching times. The resultant vector sequences split each 60° sector into eight subsectors, but each subsector has redundant vector sequences. Then, this article further quantitatively analyzes the torque ripple and ZSCC of the redundant vector sequences in the subsectors, based on which each subsector applies an optimal vector sequence. Despite the complexity of the divisions of the subsectors, this article proposes a simple carrier-based modulation scheme and the implementation of the proposed optimal vector sequences amounts to corresponding common-mode voltage (CMV) injections into the references, which only require a simple logic judgment. The theoretical analysis confirms that the proposed method yields smaller torque ripples, ZSCCs, and switching losses than existing pulsewidth modulation (PWM) schemes over the whole modulation indices. Finally, the experimental results further verify the theoretical analysis and the effectiveness of the proposed strategy.

Parallel Operation of Split-Source Inverters for PV Systems: Analysis and Modulation for Circulating Current and EMI Noise Reduction

To satisfy the ever-increasing requirement from load side and improve the power quality through harmonic content reduction, the paralleled converters' structure is seen to be an interesting solution. However, paralleled converters, in which the same dc and ac sides are shared, suffer from a major challenge related to the excessive circulating currents due to the difference in the induced common-mode voltage (CMV) in each converter. This voltage difference is due to the instantaneous potential difference between paralleled phase-legs, due to the discrepancy in circuit and control parameters of paralleled converters. Consequently, zero-sequence circulating current (ZSCC) as well as differential-mode circulating current (DMCC) shall appear between the paralleled converters. In this context, this article utilizes the interleaved pulsewidth modulation (PWM) concept for the ZSCC and DMCC reduction in paralleled split-source inverters (SSIs), where this SSI is a single-stage dc-ac converter and the prior mentioned operation and associated issues have not been investigated yet. This article describes the three-phase SSI structure and its basic operation, and shows the corresponding CMV waveform. Then, based on the shown analysis, an interleaved discontinuous PWM strategy is proposed to restrain the CMV amplitude and reduce the induced circulating currents. Furthermore, the effect of changing the modulation index and interleaving angle on the overall converter behavior has also been evaluated in case of using SSI. The analysis and simulations revealed the effectiveness of the proposed modulation strategy compared to counterparts. Finally, the shown simulation results are validated with an experimental prototype of 1 kW.

Novel space vector-based PWM strategy with minimal circulating current and line-current ripple for two parallel interleaved inverters

Existing PWM methods suffer from a tradeoff between zero-sequence circulating current (ZSCC) and line-current ripple, which are two major concerns of two parallel interleaved two-level (2L) voltage-source converters (VSCs). Thus, this paper introduces a novel space vector-based PWM strategy to reduce both line-current ripple and ZSCC. Given the redundancy of the vector combination of two parallel interleaved converters, this paper proposes eight optimal vector sequences, which simultaneously optimizes the ZSCC and the line-current ripple. Then, a carrier-based scheme is applied to yield optimal vector sequences, which simplifies the implementation procedure. Furthermore, this paper quantitatively compares both the ZSCC and the line-current ripple of the proposed method to those of existing PWM schemes. This comparison confirms that the proposed method is superior to existing PWM schemes in terms of current ripple and ZSCC. Finally, experimental results further verify the theoretical analysis and the effectiveness of the proposed strategy.

Improved Interleaved Discontinuous PWM for Zero-Sequence Circulating Current Reduction in Three-Phase Paralleled Converters

Interleaving is widely used in paralleled converters to enhance the output current quality, but subsequent circulating currents could lead to harmonic distortion and extra power losses. This article proposes an improved interleaved discontinuous pulsewidth modulation (IIDPWM) method to reduce zero-sequence circulating currents (ZSCC) in paralleled converters with common dc and ac bus. For two-paralleled converters, optimal vector sequences are selected considering minimal common-mode voltage (CMV) differences, the NTVs principle, and power losses. Furthermore, a novel carrier-based scheme is presented to implement the proposed strategy in a general case with any number of paralleled units. The 180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> carrier phase shift between two unclamped phase legs in discontinuous PWM is first applied for ZSCC reduction. Compared to existing works, the proposed strategy shows a practical value achieving good overall performance in ZSCC, output currents, switching losses, ease of use and scalability. Simulation and experimental results verified the effectiveness of the proposed IIDPWM strategy.

Design and Control Method to Suppress Resonance Circulating Current for Parallel Three-Level Rectifiers With Modified LCL Filter

The high-frequency zero-sequence circulating current (HFZSCC) is generated when the carrier phases are different in a parallel rectifiers system. Therefore, a modified <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCL</i> filter is adopted to suppress the HFZSCC. Nevertheless, the internal common mode resonance current (ICMRC) and external zero-sequence resonance circulating current (EZSRCC) are produced, which causes system instability unavoidably. Since these two issues are coupled with each other, the conventional resonance currents control methods reported so far cannot address them properly simultaneously. To suppress ICMRC and EZSRCC, a detailed model analysis of internal common mode current and zero-sequence circulating current (ZSCC) are presented, which reveal the ICMRC and EZSRCC are related to capacitor-side ZSCC (CSZSCC). Then, based on the model, in this article, the controller of CSZSCC is presented to suppress ICMRC and EZSRCC. Additionally, a closed-loop controller is designed to reject disturbances of low-frequency zero-sequence circulating current (LFZSCC). It is realized by adjusting the duty cycle of the small vectors in each pulsewidth modulation sampling period. As a result, HFZSCC, ICMRC, EZSRCC, and LFZSCC are mitigated with the proposed scheme, thus, improving the quality of the input currents. Simulation and experimental results verify the effectiveness of proposed method.

A High Performance Interleaved Discontinuous PWM Strategy for Two Paralleled Three-Phase Inverter

This article aims to obtain the optimal combination of the switching loss, maximum zero-sequence circulating current (ZSCC), and line current ripple, which benefits most of the applications. The analysis shows that the interleaved discontinues pulsewidth modulation (IDPWM) maintains the minimum switching loss and line current ripples, but it introduces a larger ZSCC. Therefore, to obtain the optimal combination of the switching loss, maximum ZSCC peak, and line current ripple, it is essential to retain the minimum switching times and the optimal line current ripple of IDPWM but further reducing its overly large ZSCC. Further analysis reveals that IDPWM includes the vector combinations with medium ZSCC change rates, resulting in the larger ZSCC. Given the redundancies of the vector combinations, this article proposes a simple matrix to modify the original modulation signals of IDPWM, eliminating the medium ZSCC change rates. The proposed PWM scheme retains the minimum line current ripple and switching times as those of IDPWM while further reducing its overly large ZSCC, as validated by analytical results as well as experimental results. Since the proposed method obtains the optimal combination among switching loss, line current ripple, and maximum ZSCC peak, we name the proposed PWM scheme a high-performance DPWM.

Robust Model Predictive Control (MPC) for large-scale PV plant based on paralleled three-phase inverters

In this contribution a robust Model Predictive Control (MPC) is proposed to enhance the power quality of a large-scale PV plant connected to the grid through Paralleled Voltage Source Inverters (PVSIs) with common AC and DC buses. Paralleling inverters allow handling high-power export and offer advantages in terms of redundancy which ensure the system reliability. However, due to the physical differences and parameter disparities between the inverters, zero sequence circulating currents will flow through it, which will disturb the performance of the system. Hence, the control goal is to regulate the currents injected into the grid, suppress the zero-sequence circulating current (ZSCC). Consequently, this study proposes an MPC algorithm that is based on optimization approach which allows minimizing circulating currents. In order to show its effectiveness and performance of the proposed control, a comparison with linear PI controller is included. In addition, design control and tuning procedure are detailed. Simulation results show the performance of the proposed controller in ensuring power quality, and suppressing circulating currents. To verify the real-time feasibility of the proposed control scheme, Hardware-In-the-Loop (HIL) setup is carried out with means of Opal-RT and dSPACE rapid prototyping systems.

Fault-tolerant control strategy for open-circuit fault of two-parallel-connected three-phase AC–DC two-level PWM converter

This paper proposes a fault-tolerant control (FTC) strategy for an open-circuit fault (OCF) of a single IGBT in a two-parallel-connected three-phase AC–DC pulse-width-modulation (PWM) converter system. In the case of the parallel-connected PWM converter system, the OCF of the IGBT causes not only DC-link voltage fluctuation and grid current distortion, but also a zero-sequence circulating current (ZSCC). Although the effect of these problems can be reduced by existing FTC methods which is used in the single PWM converter, it is difficult to totally mitigate the problems due to the ZSCC. Therefore, this paper proposes a new FTC strategy to suppress the ZSCC using the healthy converter in the parallel-connected converter. First, it is analyzed how the difference in common-mode (CM) voltage between the two converters causes ZSCC flowing inside the parallel-connected converter under the fault condition. And then, the limitation of the existing control method for ZSCC is explained. To suppress the ZSCC using the healthy converter, the proposed control method uses a d-axis voltage injection of the healthy converter which does not affect an active power control. The effectiveness of the proposed FTC strategy is verified through experimental results.

A Centralized CB-MPC to Suppress Low-Frequency ZSCC in Modular Parallel Converters

The parallel operation of three-phase converters has become an effective way to achieve modularity. However, zero-sequence circulating current (ZSCC) will appear when the multiparalleled converter modules share a common dc link. In the event that the converters have different output powers and inevitable circuit parameter mismatch, low-frequency (LF) ZSCC can be produced. To address the LF-ZSCC issues, in this article, we propose a centralized carrier-based model predictive control (CB-MPC) scheme for modular parallel converters. This control scheme can be implemented either in master converters or in a dedicate central controller. The CB-MPC can achieve both power control and LF-ZSCC elimination. In addition, with carriers adopted, interleaving and fixed device switching frequency can be easily realized. As such, the benefits of model predictive control and interleaving can be combined. Based on the ZSCC model derived in this article, the elimination of LF-ZSCC can be achieved for more than two paralleled converters when they have different output powers and/or with parameter mismatch. The effectiveness of the proposed CB-MPC has been verified by the simulation and experimental results.

Space-Vector-Based Hybrid PWM for Zero-Sequence-Circulating-Current RMS and Common Mode Voltage Reduction in Two Parallel Interleaved Two-Level Converters

This paper aims at reducing the root mean square (RMS) values of the zero-sequence circulating current (ZSCC). The analysis reveals that the ZSCC is determined by the duty ratios of the medium voltage vector and zero vector. Whereas the reference voltage fixes the duty ratio of the medium vector, the duty ratio of the zero-voltage vector depends on the distribution of the small and larger vectors, which can be used to optimize the ZSCC. As such, we propose a generalized PWM architecture, where the distribution of the active vectors is parameterized by a coefficient k. Based on this, we derive regions for k that attain the same minimal ZSCC peak. Within these regions, we further optimize k to minimize the ZSCC RMS. Depending on the reference voltage, the method selects different coefficient k for the ZSCC RMS optimizations. The proposed modulation strategy is therefore a HBSVM due to its adaptive feature in the distribution of the active vectors. The proposed HBSVM uniformly applies to the entire vector plane and is computationally affordable for mainstream microcontrollers. Finally, the experimental results validate the merits of the proposed method.

Optimal Discontinuous Space Vector PWM for Zero-Sequence-Circulating Current Reduction in Two Paralleled Three-Phase Two-Level Converter

This article proposes an optimal discontinuous pulsewidth modulation (ODPWM) strategy to reduce the zero-sequence circulating current (ZSCC) for paralleled three-phase two-level converters. While existing methods generally entail a tradeoff between the ZSCC peak and the switching losses, this article fully explores the redundancy in the vector sequences to further improve both objectives. First, we derive eight candidate vector sequences for 60° sectors, each sequence with minimal switching times and ZSCC changing rate. Second, we divide each 60° sector into 12 subsectors, each is equipped with one of the eight candidates. The comparisons show that the proposed method maintains the same maximum ZSCC peak of existing best methods while using the minimal switching times, or effectively reducing the switching loss by up to 50%; the ZSCC of the proposed method is minimal across the major modulation regions, guaranteeing a smaller loss of the common mode inductor and further reducing the semiconductor losses. We implement the proposed optimal vector sequences in a carrier-based modulation scheme, the references of which depends on the subsector. Despite the complex geometry of the subsectors, the decision procedure is simple. Finally, the experimental results confirm the effectiveness of the proposed ODPWM.

An Improved Finite-Time Control Strategy for Zero-Sequence Circulating Current Suppression of Parallel Three-Level Rectifiers

Parallel three-level rectifiers are widely employed to increase the power rating and efficiency of high-power converters. However, the zero-sequence circulating current (ZSCC) will occur due to the zero-sequence voltage difference between the parallel-operated converters, which can lead to current distortion and system loss. Therefore, an improved finite-time controller is proposed for mitigating the ZSCC in this article. A generalized model for ZSCCs in a parallel three-level rectifiers’ system is developed for designing the proposed controller. The stability against system parameter perturbation has been studied. Compared with the traditional finite-time controller and PI controller, this new control strategy can achieve better performance and stronger disturbance rejection without increasing the hardware cost. The proposed control scheme has been verified under different input currents and inductances by simulation and experimental results.

Line Current Ripple Minimization PWM Strategy With Reduced Zero-Sequence Circulating Current for Two Parallel Interleaved Three-Phase Converters

This article proposes a line-current ripple minimization pulsewidth modulation strategy with reduced zero-sequence circulating current (ZSCC) for two parallel three-phase two-level converters. We split each 60° sector into six subsectors, each applies the nearest three vectors to ensure minimal line-current ripple. To reduce the ZSCC, we further investigate all vector sequences of the nearest three vectors and derive an optimal vector sequence for each of the six subsectors. We unify all carrier sequences under a carrier-based modulation scheme with the assistance of voltage injections. The injected voltage can be computed by a simple algorithm that allows easy implementation in mainstream microcontrollers. The experimental results validate that the proposed method maintains the minimal line-current ripple while significantly reducing the ZSCC compared to the existing line current ripple minimization methods.

Dynamic Impact of Zero-Sequence Circulating Current on Modular Multilevel Converters: Complex-Valued AC Impedance Modeling and Analysis

The stability impacts of the internal control dynamics of the modular multilevel converters (MMCs) have been discussed recently. Yet, the impact of zero-sequence circulating-current (ZSCC) dynamics on the ac-side dynamics of the MMCs is hitherto unaddressed. This article develops the ac impedance model for the grid-connected MMCs by means of complex vectors and harmonic transfer-function matrices, which allows separately characterizing the dynamics of the ZSCC. Then, based on the complex-valued model, a single-input-single-output closed-loop equivalent impedance is derived for grid-connected MMCs, considering both the frequency-coupling dynamics of the MMCs and the interactions with the grid impedance, which enables a design-oriented analysis on the stability impact of the ZSCC. It is revealed that the resonant peaks in the ac impedance of the MMC are yielded due to the absence of the ZSCC control, which tends to destabilize the system in weak grids. A systematic parameter-tuning method of the ZSCC control loop is developed to guarantee the system stability. Case studies in time-domain simulations corroborate the theoretical analysis.

Phase-Disposition PWM Based 2DoF-Interleaving Scheme for Minimizing High Frequency ZSCC in Modular Parallel Three-Level Converters

This paper proposes a two-degree-of-freedom (2DoF) interleaving scheme based on phase-disposition (PD) PWM for minimizing the high-frequency zero-sequence circulating current (ZSCC) in modular interleaved three-level converters. The method incorporates an internal interleaving by phase-shifting the carriers in each individual converter, and an external interleaving by phase-shifting the carriers of the different converters. A general harmonic distribution analysis which is valid for all types of voltage source converters is carried out to simplify the evaluation of the proposed method. A comprehensive evaluation of the proposed method shows that the PD-2DoF interleaving scheme produces the lowest ZSCC maximum value as compared to existing approaches. Moreover, it can achieve comparable performances as existing methods do in terms of output quality and common mode voltage magnitude, showing a great potential for practical implementation. Simulation and experimental results are obtained to demonstrate the performance of the proposed method. Generalization of the 2DoF interleaving scheme to high-level converter is also discussed in this paper.

An Optimized Zero-Sequence Voltage Injection Method for Eliminating Circulating Current and Reducing Common Mode Voltage of Parallel-Connected Three-Level Converters

Parallel three-level inverters have attracted considerable attention due to the advantages to increase the power rating and the flexibility of power conversion systems. However, this type of configuration requires to suppress the zero-sequence circulating current (ZSCC) through either modulation or active control strategies, to avoid overloading problems of a single three-level inverter. For the operation of paralleled three-level T-type inverters, another requirement is to reduce the common mode voltage (CMV) associated with a pulsewidth modulation method. To better solve these problems simultaneously, an optimized zero-sequence voltage injection method is proposed to both reduce CMV and eliminate ZSCC for multiparallel-connected three-level inverters. A generalized CMV reduction strategy is developed, which can reduce the magnitude of CMV to one half of the value using the conventional space vector modulation. The highlight of the method is that ZSCC is eliminated by adding an optimal compensation value to the reference duty signals with lower CMV. This compensation value is calculated simply by ZSCC, duty cycles, and filter parameters. The better ZSCC suppression performance can be obtained in both steady and transient states with the proposed scheme, thus, improving the quality of currents.

Modeling and Suppression of Circulating Currents for Multi-Paralleled Three-Level T-Type Inverters

Paralleled inverters have the merits of high power rating, improved reliability, and convenient maintenance. However, zero-sequence circulating current (ZSCC) will occur and lead to current distortion and system loss. The ZSCC control is more complicated when three-level topology is utilized and paralleled number is increased. Therefore, this paper proposes a simplified ZSCC suppression scheme for multi-paralleled three-level T-type inverters (3LT2Is). A novel equivalent model is developed and the ZSCC controller based on the new model is easier to implement. Thus, the number of paralleled inverters can be increased without complicating the control scheme and the inverters could be switched on or off optionally. Besides, Feed-Forward (FF) strategy is adopted to eliminate the ZSCC spikes caused by symmetrical three-level space vector modulation. The effectiveness of the proposed control scheme is verified by both simulation and experimental results.

Space Vector Modulation Method for Simultaneous Common Mode Voltage and Circulating Current Reduction in Parallel Three-Level Inverters

Parallel three-level inverters are widely used in high-power applications for increasing the power capacity of the system. However, when multiple three-level T-type inverters are connected to a single dc bus, the zero sequence circulating current (ZSCC) will be generated. For the operation of paralleled inverters, another requirement is to reduce the common mode voltage (CMV) associated with pulsewidth modulation (PWM) method. As these two issues are mutually coupled, the conventional space vector modulation (SVM) and active control methods reported so far cannot address them properly simultaneously. To overcome this limitation, a modified SVM technique is proposed to reduce the CMV, suppress ZSCC, and balance neutral point (NP) voltage. The generating mechanism of the ZSCC with respect to modulation scheme is analyzed. Based on the analysis, the large, medium, small, zero vector modulation method is proposed for reducing ZSCC and balancing the NP voltage with reduced CMV as the same in large, medium, zero vector modulation. Furthermore, the effectiveness of the proposed method is verified by comparing its results with those of the convectional PWM. The results are obtained from simulation and experiments.

A Novel Model Predictive Control Strategy to Eliminate Zero-Sequence Circulating Current in Paralleled Three-Level Inverters

The main contribution of this paper is the proposal of a novel finite control set model predictive control (MPC)-based zero-sequence circulating current (ZSCC) elimination strategy for parallel operating three-level inverters without any modification or extra hardware on the three-level inverters. An equivalent model of the ZSCC is first developed, and the voltage differences of common-mode voltages (CMVs) among paralleled inverters as well as those of the neutral point potentials (NPPs) are proved to be the exciting sources of the ZSCC. With the analysis, an MPC-based zero CMV method (ZCMV-MPC) is presented to reduce the difference of CMVs among the paralleled inverters, meanwhile, an active NPP perturbation-based ZSCC feedback control method is proposed to further eliminate the ZSCC, that may be caused by dead-time effects and the asymmetries of both hardware and control parameters. With the proposed method, the ZSCC between paralleled inverters can be eliminated effectively, and both grid current tracking and NPP balance control can also achieve satisfactory performances. Simulation and experimental results supported the theoretical study and verified the effectiveness of the proposed scheme.

Modeling, Analysis and Evaluation of Modified Model Predictive Control Method for Parallel Three-Level Simplified Neutral Point Clamped Inverters

Parallel three-level simplified neutral point clamped inverters (3L-SNPCIs) are applied in this paper because of fewer switching devices, low harmonic, larger power capacity and more flexibility. However, the challenge of zero-sequence circulating current (ZSCC) is inevitable, which causes the output current distortion and system instability. The conventional control and modulation methods introduced by far cannot solve them properly due to the limitations of fewer voltage vectors selection. To overcome these limitations, a modified model predictive control (MMPC) strategy is proposed based on the discrete mathematical model of parallel 3L-SNPCIs. The MMPC strategy realizes circulating current suppression and neutral-point voltage balancing by selecting P-type or N-type small voltage vector. In addition, the control objectives are optimized and the implementation is simplified, which can reduce the burden of calculation and reserve the advantages of the conventional model predictive control (MPC) algorithm. The proposed control strategy can be flexibly extended to parallel multilevel inverters. The efficiency of the proposed method is proved by simulation and experimental results under various conditions.