Zed Board Research Articles

WITHDRAWN: Features of urban architecture design based on ZYNQ embedded digital image processing

The city is excellent modern buildings are an excellent historical and cultural heritage, and its conservation studies include two important things: standard-setting and protection and management strategies. With the embedded digital image processing is becoming an important part of our lives, and image processing has reached its level. These systems have created many applications, such as processing in the field of image filtering and image processing. System implementation is completed with the low-cost Zed Board ZYNQ Seven thousand Field Programmable Gate Arrays (FPGA) and Raspberry-Pi. After various image processing filters, the output will be the input image. Get a Gaussian filter, a sharpening filter, and an average filter and display these results on your Video Graphics Array (VGA) monitor. Edge detection and grayscale operations are performed on Lena's image. Chip usage is detected. Using grid-based models and software algorithms derived from image processing, effective methods have been developed to measure geometric parameters and predict radiation exchange. The proposed system is generating synthetic urban textures and integrating cellular automata. The results show that a grid-based city model can provide information for planning and design. This system accelerates the detection of lung and lung disease and can be used as a single procedure or as part of other biomedical imaging systems. Image processing systems rely on bilateral filtration, edge recognition, multi-limits, image separation, text image processing, and image labeling.

Design and Evaluation of Floating point Matrix Operations for FPGA based system design

Matrices are considered as the heart of different applications in several scientific fields such as solving electrical circuits, image processing, optimization, control systems, quantum mechanics and many more. Matrix multiplication and inverse of a matrix are considered as the two computationally expensive matrix operations. In this paper, design and evaluation of different floating-point matrix multiplication architectures/approaches and floating-point matrix inversion using model based design for FPGAs is proposed, which is an outcome of a funded project. Details about the scaling of proposed work for larger matrix sizes is also reported in the paper. The performance of proposed matrix operations is evaluated by hardware implementation of the models on a Zynq 7000 FPGA based ZED board and the results are reported.

Ultra-High Speed Switched Reluctance Motor-Generator for Turbocharger Applications

This paper proposes technical guidelines, modelling, and control of an ultra-high-speed-switched reluctance motor- generator for automotive turbo-charged assistance and energy recovery. Creation of an ideal model using electromagnetic finite element analysis and conducting a low cost/ low scale experiment is proposed. The first objective focuses on the transient simulation process. The second objective focuses on an investigation of the proposed control criteria. The modelling and analysis of a “Switched Reluctance Motor” (SRM) is an initial task for the selection of the coupled mover. Two controllers are selected for the experiment which consists of a generally low-cost solution and an optimized development board for prototyping optimization. The low-cost control solution is implemented with an Arduino Uno and an assortment of relays configured into an asymmetrical half bridge. The second controller is the “Digilent Zed Board Zynq-7000 ARM/FPGA SoC Development Board” (Zed board). ANSYS 2D, 3D modelling, data simulation for the stator and rotor are implemented. Current, voltage, and flux for all phases waveforms are included. Rotor dynamic simulation, machine transient simulations, and some other characteristics are depicted through 3D figures.

VLSI Architecture for Image Contrast Enhancement using Modified Adaptive Gamma Correction with Weighting Distribution

Background/Objectives: Due to the huge volume of data involved, it is very much challenging to design efficient contrast enhancement algorithms in real time applications. In this paper an efficient hardware is presented for image enhancement. Methods/Statistical analysis: The computation algorithms are based on the calculations of image Probability Density Function (PDF) and Cumulative Distribution Function (CDF). For better results weighted PDF and smoothed CDF computations are performed. Then the adaptive gamma correction is used for enhancing the image contrast. A compensated CDF is used as the adaptive gamma parameter. To reduce hardware complexity, approximation techniques are employed. In the modified algorithm, the bi-histogram equalization is utilized. Xilinx system generator is used for hardware co-simulation. The hardware is implemented on an FPGA based 'Zed Board'. Findings: The hardware oriented method achieves similar quality image as the software approach and the results are qualitatively and quantitatively analyzed. The PDF and CDF based computations are faster than other image processing methods. So this algorithm is suitable for real time applications. The image is found to have a better quality in the modified AGCWD method. The PSNR value also is found to be better than the normal method. But the hardware utilization of the modified algorithms is found to be higher than the normal algorithm. The bi-histogram approach is suitable to preserve the mean brightness of the original image. Applications/Improvements: Future works may modify the proposed method, for reducing the hardware requirements. Contrast enhancement is one of the crucial image processing techniques in high definition image and video applications. Image enhancement techniques find applications in LED and LCD display processing, medical image analysis etc.

FPGA Implementation of Hardware Efficient Algorithm for Image Contrast Enhancement Using Xilinx System Generator

Contrast enhancement plays an important role in generating high quality images for image processing applications, such as digital image or video photography, liquid crystal display processing, and medical image analysis. For achieving real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, a Modified Adaptive Gamma Correction with Weighting Distribution algorithm is explained for contrast enhancement. This novel hardware-oriented contrast enhancement algorithm is modeled in Xilinx System Generator and implemented in FPGA using Zed Board XC7Z020. This hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyzes. This Modified Adaptive Gamma Correction with Weighting Distribution algorithm exhibits better contrast and high PSNR value than that of the existing Adaptive Gamma Correction with Weighting Distribution algorithm.