Novel materials are being explored as charge storage media of MOS charge trapping memories to enhance their charge retention characteristic and lower their required operating voltage [1-5]. In this work, graphene nanoplatelets embedded in an ultrathin 1-nm HfO2 layer are investigated for charge storage in charge trapping MOS memory devices. The memory window achieved at different gate voltages and the energy band diagram of the memory structure are studied. The fabrication of the memory cells is conducted as follows: first a 5-nm-thick tunnel oxide Al2O3 is deposited at 250°C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system on an n+-type (111) (Antimony doped, 15-20 mΩ-cm) Si wafer. Next, 1-nm-thick HfO2 is deposited by Plasma Assisted ALD at 195°C in an Oxford FlexAL system. Then, the sample is placed on a hot plate at 110°C and 2-2.5 ml of graphene nanoplatelets solution with 0.05 mg/ml concentration are drop casted slowly using pipettes. A 1-nm-thick HfO2 is again deposited by plasma assisted ALD at 195°C followed by an 8-nm-thick Al2O3 blocking oxide deposited by ALD at 250°C. Finally, the gate contacts are created by e-beam evaporating a 400-nm-thick Al layer using a shadow mask with 10 μm feature size. An illustrative cross-section of the fabricated memory is shown in Fig. 1. In order to analyze the effect of embedding graphene nanoplatelets in the MOS memory and to quantify the stored charge at different gate voltages, high frequency (1MHz) C-Vgate measurements are conducted using an Agilent B1505A Semiconductor Device Parameter Analyzer to measure the programmed and erased characteristics of the fabricated memory devices as depicted in Fig. 2. The memory cells showed a 1.35 V threshold voltage (Vt) shift upon sweeping the gate voltage from -5 V forward to 5 V then backwards. At -7/7 V gate sweeping voltage, more charging is observed through the higher 3 V Vt shift. The results show that the memory is being programmed by storing electrons in the graphene nanoplatelets as shown by the shift of the programmed state in the positive direction at higher gate sweeping voltages. At 7/-7 V gate sweeping voltage and with a 3 V Vt shift, the charge trapping density in the graphene nanoplatelets is calculated [4] and found to be 1.54 ×1013 cm-3. Using the reported band offsets and band gaps of Al2O3, HfO2, and graphene, the energy band diagram of the memory is constructed as shown in Fig. 3 [6]. The conduction band offset between Si and tunnel oxide is smaller than the valence band offset (ΔEC = 2.44 eV < ΔEV = 3.24 eV), thus the electrons tunneling probability is expected to be higher which confirms the observed electrons storage. In addition, due to the large work-function of graphene, a deep quantum well is formed where electrons can be stored. In fact, the conduction band offset between charge trapping layer and tunnel oxide is very large (ΔEC = 2.99 eV) which exponentially reduces the leakage of stored electrons in the graphene nanoplatelets. Moreover, the addition of the high-dielectric constant (қ=20) HfO2 layer is expected to further reduce the leakage of stored charges. Finally, the results presented in this work indicate that graphene has potential in future low-power charge trapping memory devices. Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 111A015, 112M004, 112E052 and 113M815. A.K.O. acknowledges support from the Turkish Academy of Sciences Distinguished Young Scientist Award (TUBA GEBIP).
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Sep 28, 2015
Open Access
Nazek El-Atab + 3