Yield Stress Of Copper Research Articles

A Novel Lining Method for Eliminating Plastic Deformation and Protrusion of Copper in Cu-TSV Using FEM Analysis

Employing FEM analysis, a new lining method was invented to prevent plastic deformation and protrusion of copper in Cu-TSV after experiencing a thermal cycle (heating up from room temperature to 300°C and then cooling down to room temperature). Using this technique, thermal stresses exerted to the via were reduced to below the yield stress of copper, preventing copper from undergoing plastic deformation. Consequently, not only was the height of copper protrusion at 300°C decreased, but there was no extrusion bulge or dishing at the end of thermal cycle. Compared with traditional titanium barriers, copper protrusion at the end of thermal cycle decreased from 208.2 nm to 3.4 nm after the first thermal cycle and from 325.2 nm to (again) 3.4 nm after 10 successive thermal cycles.

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensional system in package (3D SiP) under device operation condition were discussed. A large scale simulator, ADVENTURECluster® based on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV.

Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.

602 シリコン貫通ビア構造を有する三次元積層半導体チップの熱応力(OS6-1 シリコン貫通ビア技術と強度信頼性)

The feasibility for cooling and mechanical strength around TSV(Jhrough Silicon Via) structures in 3D SiP(System in Package) were discussed in this study with large scale simulator based on finite element method, ADVENTURECluster[○!R]. Required cooling efficiency for the heat sink of the SiP was shown, and a liquid cooling system has to be considered. Thermal stresses in the chip were shown by elastic stress analysis in TSV were like hydrostatic pressure and the magnitude of the equivalent stress was lower than yield stress of copper. However, it was noticed that that the axial stress in TSV, that was 100 MPa, cannot be ignored. In case that there is a defect in TSV, simulation result showed that the stress applied to Si chip was reduced by defect. However, TSV may be broken due to stress concentration. Unsteady thermal conduction analysis and inelastic thermal stress analysis are necessary to discuss the problem in more detail