XOR-XNOR Circuit Research Articles

Low Power and Delay Efficient 4x4 Array Multiplier Using 20T Hybrid Adder in 90nm Technology

In this paper, the 4x4 array multiplier was designed and its power Delay Product (PDP) was analyzed. An array of full adders and half adders is used in an array multiplier, a combinational circuit, to multiply two binary values. The total power consumed by the array multiplier can be minimized by introducing a hybrid adder which constitutes 20T. In the 20T hybrid adder maximum power consumption is mostly dependent on the performance of the 10T XOR-XNOR circuit. As a result, it offers both full swing output and good capabilities without the need for an external inverter. Therefore, the array multiplier was designed by a hybrid adder instead of a conventional adder circuit to achieve low power and delay efficient multiplier circuit. The hybrid adder circuit outperforms its counterparts showing that PDP reduces 18% more than available conventional full adders. Using 90nm CMOS technology, the suggested circuits' performance is evaluated by stimulating them in a cadence virtuoso environment.

WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

In this paper, we propose a hybrid full-swing adder (HFSA) circuit that uses the hybrid full-swing logic (HFSL) technique, which consists of 20 transistors. This circuit relies heavily on a 12-transistor XOR-XNOR circuit to optimize the area and power. Our novel XOR-XNOR circuit plays a crucial role in achieving high-efficiency HFSA circuits. It integrates 2-to-1 multiplexers, pass transistor logic, and inverters to deliver glitch-free full-swing outputs. We compared the efficiency and practicality of our design with those of 10 alternatives by considering their performances and characteristics. Our novel XOR-XNOR circuit surpassed its counterparts with an exceptional chip area reduction of 14.14–28.01 %, an average power of 2.44 μW, and remarkably low delays of 25.88 and 24.87 ps. Notably, the proposed full adder achieved a chip area reduction of 11.30–49.69 %, 3.582 μW power, and a 72.66 ps delay. It emphasizes large-scale structures, such as 4-bit to 64-bit full adders, implemented using cascaded designs with a novel ripple carry adder. Using multipoint and Monte Carlo analysis in the ADEXL design suite to ensure the reliability of all circuits using the Cadence Virtuoso with the GPDK45 nm technology. The proposed method is an alternative to high-speed electronic systems with potential benefits.

High-Speed Hybrid Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell Using 18-nm FinFET Technology

Abstract: The Portable electronic gadgets have turned into a major part of life. Electronic gadgets predominantly consist of arithmetic units. A full adder is an important part of arithmetic units like multipliers. In order to enhance the rate and efficiency of such systems, it is worthwhile to design a FA that has higher rates of speed and low consumption of power. A Full adder circuit is frequently implemented using a hybrid logic approach. This work proposes a 10T XOR-XNOR circuit which shows improved delay performance. The suggested circuit's performance is determined by modeling that circuit in a virtuoso platform powered by cadence by using 18-nm FinFET technology. Additionally, here four distinct designs of a full adder are presented by making use of the proposed XOR-XNOR circuit and the available sum and carry modules. These circuits show an improved PDP when simulated using FinFET technology than CMOS technology.

A Comparative Performance Analysis of CMOS XOR XNOR Circuits

New XOR-XNOR circuit modes are proposed to improve speed and power as these circuits are the building blocks of multiple arithmetic circuits. This project evaluates and compares the performance of various XOR-XNOR circuits. The performance of XOR-XNOR circuits is tested by comparing the simulation results obtained with Electric VLSI. The mimicry results show which region has the lowest PDP and EDP performance, the most energy efficient and fastest compared to the best available XOR-XNOR circuits.

Design and performance analysis of full adder using 6-T XOR-XNOR cell

In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product).

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

Low Power and Area Efficient 4-2 Compressor for Signal Processing Applications

In this paper, two performance metrics power and delay are estimated for various XOR-XNOR circuits and Multiplexer for designing 4-2 compressor. The main objective is to design an energy efficient compressor for computing applications in FIR filter. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 4-2 compressors consist of six blocks out of which two XOR-XNOR blocks and four MUX blocks. The average power, delay and energy consumed by the proposed compressor which is based on 5T XOR-XNOR and GDIMUX design is 85.72 nW, 62.53 pS and 5.36 aJ respectively

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of xor–xnor circuit. In this article, a high-speed, low-power 10-T xor–xnor circuit is proposed, which provides full swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. The proposed circuit reduces the power delay product (PDP) at least by 7.5% than that of the available xor–xnor modules. Four different designs of FAs are also proposed in this article utilizing the proposed xor–xnor circuit and available sum and carry modules. The proposed FAs provide 2%–28.13% improvement in terms of PDP than that of other architectures. To measure the driving capabilities, the proposed FAs are embedded in 2-, 4-, and 8-bit cascaded full adder (CFA) structures. Results show that two of the proposed FAs provide the best performance for a higher number of bits among all the FAs.

Analysis Of Low Power And Reliable XOR-XNOR Circuit For High Speed Applications

This paper presents a comprehensive study of different types of XOR-XNOR circuits. Our main focus is to characterise the XOR-XNOR combinational circuit design using six transistors for low power applications. The six transistor XOR-XNOR circuit can be simulated using 45nm CMOS technology in cadence virtuoso using foundry files. The simulation results demonstrates, parameters such as power, delay and power delay product(PDP) at different voltages ranging from 0.4 to 1v respectively. From the obtained results it clearly indicates the proposed design has low power consumption and full voltage swing.

Power Efficient Design of Polar Code

Polar codes are the family of the codes which are first ones to achieve channel capacity of any binary discrete memory less channel (B-DMC) with an explicit construction. The method relates with polar codes, channel polarization and encoding & decoding of polar code is considered that in the live structure of polar code when BER gets increase, channel capacity is satisfied but overall power of data transmition in channel gets increase. So here in this analysis the main issue is related with the power consumption. Encoding & decoding construction of polar codes is based on XOR-XNOR gates. The XOR-XNOR circuits’ design which uses 6 transistors instead of conventional structure is designed and it is suitable for lowvoltage and low-power application by achieving lower delay, power consumption and power-delay product (PDP).So by using this design phenomenon of XOR-XNOR gate it is possible to construct power efficient encoding and decoding of polar codes.

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks for many arithmetic circuits. This paper contrasts and evaluates the performance of conventional CMOS and FinFET based XOR-XNOR circuit design. It is based on the study of high speed, low power, and small area in XOR-XNOR digital circuits. The proposed FinFET based XOR and XNOR circuits have been designed using Cadence VIRTUOSO Tool applying voltage supply of 0.2 to 1.2 voltages, with temperature at 27 0 C and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technology. Simulation results exhibit low power, delay, power, delay product (PDP), and average dynamic power consumption.

A High-Performance Full Adder Circuit Based on a Novel 7-T XOR-XNOR Cell

A high performance full adder circuit with full voltage-swing based on a novel 7-transistor xor-xnor cell is proposed in this paper. In our design, we exploit a novel 7-transistor xor-xnor circuit with a signal level restorer in a feedback path to settle the threshold voltage loss problem. Then we present a new high-performance 1-bit full adder based on the designed xor-xnor cell, pass-transistors and transmission gates. The simulation results prove that, compared with other designs in literature, the proposed full adder shows its superiority for less power dissipation, lower critical path delay and smaller power-delay product, and still provides full voltage swing in all nodes of the circuit.

A New Cell Design Methodology for Balanced XOR–XNOR Circuits for Hybrid-CMOS Logic

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. Our methodology is based on using different basic cells and optimizations. We start with selecting a basic cell including two independent inputs and two complementary outputs. Next we combine this basic cell with various correction and optimization techniques to build a perfect XOR-XNOR circuit with full swing operation. Using this new design method, we introduce 32 balanced XOR-XNOR circuits of which some have been previously presented. The energy optimized circuits are designed using 0.13-μm CMOS technology. We improve power-delay product from 24% to 49% for different supply voltages. Simulation results show that the proposed circuits exhibit better performances, power, and PDP compared to previously suggested circuits. We evaluate our proposed circuits using SPEC2000 benchmarks.

New Design Methodologies for High Speed Low Power XOR-XNOR Circuits

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18µm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature. Keywords—Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits. I. INTRODUCTION HILE the growth of the electronics market has driven the VLSI industry towards very high integration density and system on chip designs and beyond few GHz operating frequencies, critical concerns have been arising to the severe increase in power consumption and the need to further reduce it. Moreover, with the explosive growth the demand and popularity of portable electronics is driving designers to strive for smaller silicon area, higher speeds, longer battery life, and more reliability. Power is one of the premium resources a designer tries to save when designing a system. The XOR- XNOR circuits are basic building blocks in various circuit especially-Arithmetic circuits (Full adder, and multipliers), Compressors, Comparators, Parity Checkers, Code converters, Error-detecting or Error-correcting codes, and Phase detector circuit in PLL. The performance of the complex logic circuits is affected by the individual performance of the XOR-XNOR circuits that are included in them (1)-(6). Therefore, careful design and analysis is required for XOR-XNOR circuits to obtained -full output

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders

High performance 5 : 2 compressor architectures

Fast arithmetic circuits are key elements of high performance computers and data processing systems. In the majority of these applications, multipliers have been a critical and obligatory component in dictating the overall circuit performance when constrained by power consumption and computation speed. Compressors are a critical component of the multiplier circuit, which greatly influence the overall multiplier speed. The authors propose two novel high performance 5 : 2 compressor architectures. The main objective of their designs is to limit the carry propagation to a single stage, thereby reducing the overall propagation delay. The designs are compared with the best one in the literature in terms of delay and are found to have lower values. The analytical techniques use the node capacitances in the signal delay paths to identify the worst delay path. The architectures are implemented with various XOR–XNOR circuits to identify the best one in terms of power and delay. The simulation results of the proposed architectures show lower power and 25% improvement in speed compared to the best architecture reported in the literature for supply voltages ranging from 1.5 V to 3.3 V.