Abstract
Abstract: The Portable electronic gadgets have turned into a major part of life. Electronic gadgets predominantly consist of arithmetic units. A full adder is an important part of arithmetic units like multipliers. In order to enhance the rate and efficiency of such systems, it is worthwhile to design a FA that has higher rates of speed and low consumption of power. A Full adder circuit is frequently implemented using a hybrid logic approach. This work proposes a 10T XOR-XNOR circuit which shows improved delay performance. The suggested circuit's performance is determined by modeling that circuit in a virtuoso platform powered by cadence by using 18-nm FinFET technology. Additionally, here four distinct designs of a full adder are presented by making use of the proposed XOR-XNOR circuit and the available sum and carry modules. These circuits show an improved PDP when simulated using FinFET technology than CMOS technology.
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