Xilinx Virtex-II Pro Field Programmable Gate Arrays Research Articles

Cloud Computing-Based Non-Invasive Glucose Monitoring for Diabetic Care

Near infrared photoacoustic spectroscopy is utilized for the development of a continuous non-invasive glucose monitoring system for diabetics. A portable embedded system for taking photoacoustic measurements on tissues to estimate glucose concentration is implemented using field programmable gate array (FPGA). The back-end architecture for high-speed data acquisition and de-noising of photoacoustic measurements operates at 274.823 MHz on a Xilinx Virtex-II Pro FPGA. The glucose measurement technique is verified in vitro on glucose solutions and in vivo on tissues, with photoacoustic signal amplitude varying linearly with sample glucose concentration. A kernel-based regression algorithm using multiple features of the photoacoustic signal is used to estimate glucose concentration from photoacoustic measurements. The calibration algorithm provides a superior performance over previous efforts with a mean absolute relative difference of 8.84% and Clarke Error Grid distribution of 92.86% and 7.14% over Zones A and B of the grid. A cloud computing platform for automated monitoring of blood glucose levels is proposed to enable individuals with diabetes to connect with doctors and caretakers. The developed system is connected to the cloud service using a mobile device, which facilitates implementation of computationally intensive calibration tasks and the storage and analysis of measurement data for treatment and monitoring.

A new intelligent hardware implementation based on field programmable gate array for chaotic systems

In the present study, a new intelligent hardware implementation was developed for chaotic systems by using field programmable gate array (FPGA). The success and superior properties of this new intelligent hardware implementation was shown by applying the Modified Van der Pol–Duffing Oscillator Circuit (MVPDOC). The validation of intelligent system model was tested with both software and hardware. For this purpose, initially the intelligent system model of MVPDOC was obtained by using the wavelet decompositions and Artificial Neural Network (ANN). Then, the intelligent system model obtained has been written in Very High Speed Integrated Circuit Hardware Description Language (VHDL). In the next step, these configurations have been simulated and tested under ModelSim Xilinx software. And finally the best configuration has been implemented under the Xilinx Virtex-II Pro FPGA (XC2V1000). Furthermore, the High Personal Simulation Program with Integrated Circuit Emphasis (HSPICE) simulation of MVPDOC has been carried out under ModelSim Xilinx software for comparison with proposed intelligent system. The results obtained show that the proposed intelligent system simulation has much higher speed in comparison with HSPICE simulation.

POSE: Design of Hardware-Friendly Particle-Based Observation Selection PHD Filter

Particle probability hypothesis density (PHD) filtering is a promising technology for the multitarget-tracking problem. Traditional particle PHD filter solutions usually have high computational complexity, and the lack of dedicated hardware has seriously limited their usages in real-time industrial applications. The hardware implementation difficulty of the particle PHD filtering in field-programmable gate array (FPGA) platforms lies in that the number of observations for filtering is time varying while the number of parallel processing units in circuit is fixed. To overcome this challenge, we propose a novel particle-based observation selection (POSE) PHD filter algorithm and its hardware implementation in this paper. Specifically, we opportunistically select a fixed number of observations out of a varying number of observations for filtering, where the approximation error is proved to be negligible by adapting the circuit budget to the environment accordingly. To implement the proposed POSE PHD filter, the hardware design issues are addressed in depth. Extensive simulations demonstrate that the POSE PHD filter has a comparable performance with the traditional one while its hardware implementation challenge is overcome. The hardware experiment results of the POSE PHD filter on a Xilinx Virtex-II Pro FPGA platform match the simulation ones well. Furthermore, the execution time of the implemented hardware circuit is evaluated, and the results show that it can achieve a processing rate of 6.892 kHz with a 50-MHz system clock.

Field-Programmable Gate Array (FPGA) Implementation of Lapped Biorthogonal Transform for JPEG XR Compression

This paper describes the hardware implementation of Lapped Biorthogonal Transform (LBT) on Field-Programmable Gate Array (FPGA) for JPEG XR Image compression. The implementation is based on dividing image into 128×128 dimension tiles with each tile processed independently. Two main operations that is, overlap pre-filtering and forward core transform are applied on each tile. The proposed design has small memory requirement due to fix 128×128 tile size processing. The hardware design is tested on Xilinx Virtex-II Pro FPGA. The design utilizes 262,144 memory bits, 5824 number of slices and maximum speed is 107.308 MHz. Key words: Lapped Biorthogonal Transform (LBT), Field-Programmable Gate Array (FPGA), image compression, implementation.

A contribution to the reduction of the dynamic power dissipation in the turbo decoder

In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the power consumption in the turbo decoder. The main idea is based on re-encoding technique combined with dummy insertion during the iterative decoding process. This technique, named “toward zero path” (TZP) helps in reducing the state transition activity of the Max-Log-MAP algorithm by trying to maintain the survivor path on the ‘zero path’ of the trellis. The design of a turbo decoder based on the TZP technique, associated with different power reduction technique (saturation of state metrics, stoping criterium) is described. The resulting turbo decoder was implemented onto a Xilinx VirtexII-Pro field-programmable gate array (FPGA) in a digital communication experimental setup. Performance and accurate power dissipation measurements have been done thanks to dynamic partial reconfiguration of the FPGA device. The experimental results have shown the interest of the different contributions for the design of turbo decoders.

Feat Of Submerged Scheme Relevance In Power Pc Processor Based Fpga Using Fpga Ip Cores

Under water systems use processor based rooted systems to provide control and guidance to the under water vehicles. They obtain target and vehicle dynamics data from sensors and gyros, and process this data as per control and guidance algorithms to generate control and guidance parameters to the actuation system. Traditionally x86 families are being used in these systems in amassing to memory, I/Os and other peripherals being on the card. The recent developments in FPGA (Field Programmable Gate Array) technology has made pavement to use superior FPGAs with IP cores to develop under water systems. The modern FPGA devices include 32-bit Power PC processor, memory blocks and programmable area to comprise peripheral blocks. Under water systems developed out of the FPGA cores are definitely have several advantages like, saving the card size (FPGA accommodates several of the components in addition to the processor), flexibility to adopt changes in design (as FPGA can be programmed by the end user), preventing obsolescence of components. Building an under water systems based on FPGA IP cores is an innovative and hottest technological demonstration with several advantages to prophesy. The present work describes the dwindling in power consumption and size of the Under Water System. This work will also be productive to CSS Division of NSTL in designing and miniaturizing embedded systems such as MCS, MDAC etc. used in marine systems. The present work describes the mellowness of under water system relevance in Power PC Based FPGA using FPGA IP Cores. This work includes understanding the design flow of EDK and learns about various IP Cores Provided by Xilinx EDK 10.1. The underwater system application has been implemented in ‘C’ language by using Xilinx Device Drivers. A custom logic in VHDL has been developed for truncating extra bits of ADC. In Xilinx ISE10.1 project navigator the developed VHDL Code has been integrated with C. The combined bit file generated has been downloaded into Xilinx Virtex-II Pro FPGA Proto Board.

A Hardware-Accelerated Quantum Monte Carlo framework (HAQMC) for N-body systems

Interest in the study of structural and energetic properties of highly quantum clusters, such as inert gas clusters has motivated the development of a hardware-accelerated framework for Quantum Monte Carlo simulations. In the Quantum Monte Carlo method, the properties of a system of atoms, such as the ground-state energies, are averaged over a number of iterations. Our framework is aimed at accelerating the computations in each iteration of the QMC application by offloading the calculation of properties, namely energy and trial wave function, onto reconfigurable hardware. This gives a user the capability to run simulations for a large number of iterations, thereby reducing the statistical uncertainty in the properties, and for larger clusters. This framework is designed to run on the Cray XD1 high performance reconfigurable computing platform, which exploits the coarse-grained parallelism of the processor along with the fine-grained parallelism of the reconfigurable computing devices available in the form of field-programmable gate arrays. In this paper, we illustrate the functioning of the framework, which can be used to calculate the energies for a model cluster of helium atoms. In addition, we present the capabilities of the framework that allow the user to vary the chemical identities of the simulated atoms. Program summary Program title: Hardware Accelerated Quantum Monte Carlo (HAQMC) Catalogue identifier: AEEP_v1_0 Program summary URL: http://cpc.cs.qub.ac.uk/summaries/AEEP_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 691 537 No. of bytes in distributed program, including test data, etc.: 5 031 226 Distribution format: tar.gz Programming language: C/C++ for the QMC application, VHDL and Xilinx 8.1 ISE/EDK tools for FPGA design and development Computer: Cray XD1 consisting of a dual-core, dualprocessor AMD Opteron 2.2 GHz with a Xilinx Virtex-4 (V4LX160) or Xilinx Virtex-II Pro (XC2VP50) FPGA per node. We use the compute node with the Xilinx Virtex-4 FPGA Operating system: Red Hat Enterprise Linux OS Has the code been vectorised or parallelized?: Yes Classification: 6.1 Nature of problem: Quantum Monte Carlo is a practical method to solve the Schrödinger equation for large many-body systems and obtain the ground-state properties of such systems. This method involves the sampling of a number of configurations of atoms and averaging the properties of the configurations over a number of iterations. We are interested in applying the QMC method to obtain the energy and other properties of highly quantum clusters, such as inert gas clusters. Solution method: The proposed framework provides a combined hardware–software approach, in which the QMC simulation is performed on the host processor, with the computationally intensive functions such as energy and trial wave function computations mapped onto the field-programmable gate array (FPGA) logic device attached as a co-processor to the host processor. We perform the QMC simulation for a number of iterations as in the case of our original software QMC approach, to reduce the statistical uncertainty of the results. However, our proposed HAQMC framework accelerates each iteration of the simulation, by significantly reducing the time taken to calculate the ground-state properties of the configurations of atoms, thereby accelerating the overall QMC simulation. We provide a generic interpolation framework that can be extended to study a variety of pure and doped atomic clusters, irrespective of the chemical identities of the atoms. For the FPGA implementation of the properties, we use a two-region approach for accurately computing the properties over the entire domain, employ deep pipelines and fixed-point for all our calculations guaranteeing the accuracy required for our simulation.

High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware

Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid advances in technology, hardware acceleration of linear algebra applications using FPGAs (Field Programmable Gate Arrays) has become feasible. In this paper, we propose FPGA-based designs for several basic linear algebra operations, including dot product, matrix-vector multiplication, matrix multiplication and matrix factorization. By identifying the parameters for each operation, we analyze the trade-offs and propose a high-performance design. In the implementations of the designs, the values of the parameters are determined according to the hardware constraints, such as the available chip area, the size of available memory, the memory bandwidth, and the number of I/O pins. The proposed designs are implemented on Xilinx Virtex-II Pro FPGAs. Experimental results show that our designs scale with the available hardware resources. Also, the performance of our designs compares favorably with that of general-purpose processor based designs. We also show that with faster floating-point units and larger devices, the performance of our designs increases accordingly.

FPGA acceleration of a quantum Monte Carlo application

Quantum Monte Carlo methods enable us to determine the ground-state properties of atomic or molecular clusters. Here, we present a reconfigurable computing architecture using Field Programmable Gate Arrays (FPGAs) to accelerate two computationally intensive kernels of a Quantum Monte Carlo (QMC) application applied to N-body systems. We focus on two key kernels of the QMC application: acceleration of potential energy and wave function calculations. We compare the performance of our application on two reconfigurable platforms. Firstly, we use a dual-processor 2.4 GHz Intel Xeon augmented with two reconfigurable development boards consisting of Xilinx Virtex-II Pro FPGAs. Using this platform, we achieve a speedup of 3× over a software-only implementation. Following this, the chemistry application is ported to the Cray XD1 supercomputer equipped with Xilinx Virtex-II Pro and Virtex-4 FPGAs. The hardware-accelerated application on one node of the high performance system equipped with a single Virtex-4 FPGA yields a speedup of approximately 25× over the serial reference code running on one node of the dual-processor dual-core 2.2 GHz AMD Opteron. This speedup is mainly attributed to the use of pipelining, the use of fixed-point arithmetic for all calculations and the fine-grained parallelism using FPGAs. We can further enhance the performance by operating multiple instances of our design in parallel.

Design tradeoff analysis of floating-point adders in FPGAs

With gate counts of ten million, field-programmable gate arrays (FPGAs) are becoming suitable for floating-point computations. Addition is the most complex operation in a floating-point unit and can cause major delay while requiring a significant area. Over the years, the VLSI community has developed many floating-point adder algorithms aimed primarily at reducing the overall latency. An efficient design of the floating-point adder offers major area and performance improvements for FPGAs. Given recent advances in FPGA architecture and area density, latency has become the main focus in attempts to improve performance. This paper studies the implementation of standard; leading-one predictor (LOP); and far and close datapath (2-path) floating-point addition algorithms in FPGAs. Each algorithm has complex sub-operations which contribute significantly to the overall latency of the design. Each of the sub-operations is researched for different implementations and is then synthesized onto a Xilinx Virtex-II Pro FPGA device. Standard and LOP algorithms are also pipelined into five stages and compared with the Xilinx IP. According to the results, the standard algorithm is the best implementation with respect to area, but has a large overall latency of 27.059 ns while occupying 541 slices. The LOP algorithm reduces latency by 6.5% at the cost of a 38% increase in area compared to the standard algorithm. The 2-path implementation shows a 19% reduction in latency with an added expense of 88% in area compared to the standard algorithm. The five-stage standard pipeline implementation shows a 6.4% improvement in clock speed compared to the Xilinx IP with a 23% smaller area requirement. The five-stage pipelined LOP implementation shows a 22% improvement in clock speed compared to the Xilinx IP at a cost of 15% more area.