Xilinx Virtex-5 Field Programmable Gate Array Research Articles

Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames

Radiation-induced multiple bit upsets (MBUs) are a major reliability concern in nanoscale technology nodes. Occurrence of such errors in the configuration frames of a field-programmable gate array (FPGA) device permanently affects the functionality of the mapped design. Periodic configuration scrubbing combined with a low-cost error correction scheme is an efficient approach to avoid such a permanent effect. Existing techniques employ error correction codes with considerably high overhead to mitigate MBUs in configuration frames. In this paper, we present a low-cost error-detection code to detect MBUs in configuration frames as well as a generic scrubbing scheme to reconstruct the erroneous configuration frame based on the concept of erasure codes. The proposed scheme does not require any modification to the FPGA architecture. Implementation of the proposed scheme on a Xilinx Virtex-6 FPGA device shows that the proposed scheme can detect 100% of MBUs in the configuration frames with only 3.3% resource occupation, while the recovery time is comparable with the previous schemes.

Protection of heterogeneous architectures on FPGAs: An approach based on hardware firewalls

Embedded systems are parts of our daily life and used in many fields. They can be found in smartphones or in modern cars including GPS, light/rain sensors and other electronic assistance mechanisms. These systems may handle sensitive data (such as credit card numbers, critical information about the host system and so on) which must be protected against external attacks as these data may be transmitted through a communication link where attackers can connect to extract sensitive information or inject malicious code within the system. This work presents an approach to protect communications in multiprocessor architectures. This approach is based on hardware security enhancements acting as firewalls. These firewalls filter all data going through the system communication bus and an additional flexible cryptographic block aims to protect external memory from attacks. Benefits of our approach are demonstrated using a case study and some custom software applications implemented in a Field-Programmable Gate Array (FPGA). Firewalls implemented in the target architecture allow getting a low-latency security layer with flexible cryptographic features. To illustrate the benefit of such a solution, implementations are discussed for different MPSoCs implemented on Xilinx Virtex-6 FPGAs. Results demonstrate a reduction up to 33% in terms of latency overhead compared to existing efforts.

High-Speed Transmission and Mass Data Storage Solutions for Large-Area and Arbitrarily Structured Fabrication through Maskless Lithography

This paper presents the implementation aspects and design of high-speed data transmission in laser direct-writing lithography. With a single field programmable gate array (FPGA) chip, mass data storage management, transmission, and synchronization of each part in real-time were implemented. To store a massive amount of data and transmit data with high bandwidth, a serial advanced technology attachment (SATA) intellectual property (IP) was developed on Xilinx Virtex-6 FPGA. In addition, control of laser beam power, collection of status read back data of the lithography laser through an analog-to-digital converter, and synchronization of the positioning signal were implemented on the same FPGA. A data structure for each unit with a unique exposure dose and other necessary information was established. Results showed that the maximum read bandwidth (240 MB/s) and maximum write bandwidth (200 MB/s) of a single solid-state drive conform to the data transmission requirement. The total amount of data meets the requirement of a large-area diffractive element approximately 102 cm2. The throughput has been greatly improved at meters per second or square centimeter per second. And test results showed that data transmission meets the requirement of the experiment.

Implementation of Menezes Vanstone elliptical curve cryptography algorithm using matrix mapping method

This paper proposes an approach to encrypt data (message) using Menezes Vanstone encryption and decryption algorithm based on elliptic curve (EC). In traditional elliptic curve cryptography (ECC) algorithm, the generator point is published along with other domain parameters. The certificate authority (CA) shares the point between the source and destination. An intruder launching man-in-middle (MIM) attack could crack the public key, leading to a security breach in the network. This paper discusses techniques, which make use of a hidden generator point to overcome MIM attack in the Menezes Vanstone elliptical curve cryptosystem (MVECC). The hidden generator point from two different curves is added to get a common generator point. Mapping is then performed with American Standard Code for Information Interchange (ASCII) characters and double mapped using matrix mapping to enhance the encryption. The MVECC encryption and decryption is implemented on field programmable gate array (FPGA) which is written in Verilog Hardware Description Language (HDL). The synthesis results obtained shows that the minimum period is 92.713 ns and maximum frequency is 10.786 MHz for MVECC over GF (p) on Xilinx Virtex-5 (XC5VLX50T-1FF1136) FPGA Board.

Implementation of Menezes Vanstone elliptical curve cryptography algorithm using matrix mapping method

This paper proposes an approach to encrypt data (message) using Menezes Vanstone encryption and decryption algorithm based on elliptic curve (EC). In traditional elliptic curve cryptography (ECC) algorithm, the generator point is published along with other domain parameters. The certificate authority (CA) shares the point between the source and destination. An intruder launching man-in-middle (MIM) attack could crack the public key, leading to a security breach in the network. This paper discusses techniques, which make use of a hidden generator point to overcome MIM attack in the Menezes Vanstone elliptical curve cryptosystem (MVECC). The hidden generator point from two different curves is added to get a common generator point. Mapping is then performed with American Standard Code for Information Interchange (ASCII) characters and double mapped using matrix mapping to enhance the encryption. The MVECC encryption and decryption is implemented on field programmable gate array (FPGA) which is written in Verilog Hardware Description Language (HDL). The synthesis results obtained shows that the minimum period is 92.713 ns and maximum frequency is 10.786 MHz for MVECC over GF (p) on Xilinx Virtex-5 (XC5VLX50T-1FF1136) FPGA Board.

Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves

The architecture and the implementation of a high-performance scalable elliptic curve cryptography processor (ECP) are presented. The proposed ECP is able to support all five prime field elliptic curves recommended by the National Institute of Standards and Technology (NIST). The design takes advantage of the high-performance capabilities of the DSP48E slices available in Xilinx field-programmable gate arrays (FPGAs) to achieve high speed and low hardware resource utilization. The proposed design parallelizes the underlying prime field operations to reduce the latency of the elliptic curve point multiplication (ECPM) operation. Prime field inversion is performed efficiently using the same arithmetic blocks as the ones used for prime field multiplication and addition/subtraction. To the best of the authors' knowledge, the proposed scalable ECP is the fastest and smallest ECP that can support all five NIST recommended prime curves without the need to reconfigure the hardware. It can compute the ECPM between 1.709 and 28.04 ms using a Xilinx Virtex-5 FPGA.

TOT measurement implemented in FPGA TDC**Supported by National Natural Science Foundation of China (11079003, 10979003)

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays (FPGAs), FPGA time-to-digital converters (TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold (TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.

An FPGA-Based Multicore System for Real-Time Bearing Fault Diagnosis Using Ultrasampling Rate AE Signals

The demand for online fault diagnosis has recently increased in order to prevent severe unexpected failures in machinery. To address this issue, this paper first proposes a comprehensive bearing fault diagnosis algorithm, which consists of fault signature extraction through time-frequency analysis and one-against-all multiclass support vector machines in order to make reliable decisions. In addition, acoustic emission (AE) signals sampled at 1 MHz are used for the early identification of bearing failures. Despite the fact that the proposed fault diagnosis methodology shows satisfactory classification accuracy, its computation complexity limits its use in real-time applications. Therefore, this paper also presents a high-performance multicore architecture, including 64 processing elements operating at 50 MHz in a Xilinx Virtex-7 field-programmable gate array device to support online fault diagnosis. The experimental results indicate that the multicore approach executes 1339.3x and 1293.1x faster than the high-performance Texas Instrument (TI) TMS320C6713 and TMS320C6748 digital signal processors (DSPs), respectively, by exploiting the massive parallelism inherent in the bearing fault diagnosis algorithm. In addition, the multicore approach outperforms the equivalent sequential approach that runs on the TI DSPs by substantially reducing the energy consumption.

Reliable Radix-4 Complex Division for Fault-Sensitive Applications

Complex division is commonly used in various applications in signal processing and control theory including astronomy and nonlinear RF measurements. Nevertheless, unless reliability and assurance are embedded into the architectures of such structures, the sub-optimal (and thus erroneous) results could undermine the objectives of such applications. As such, in this paper, we present schemes to provide complex number division architectures based on Sweeney, Robertson, and Tocher-division with error detection mechanisms. Different error detection architectures are proposed in this paper which can be tailored based on the eventual objectives of the designs in terms of area and time requirements, among which we pinpoint carefully the schemes based on recomputing with shifted operands to be able to detect faults based on recomputations for different operands in addition to the unified parity (simplified detecting code) and hardware redundancy approach. The design also implements a minimized look up table approach which favors in error detection based designs and provides high fault coverage with relatively-low overhead. Additionally, to benchmark the effectiveness of the proposed schemes, extensive error detection assessments are performed for the proposed designs through fault simulations and field-programmable gate array (FPGA) implementations; the design is implemented on Xilinx Spartan-6 and Xilinx Virtex-6 FPGA families.

A low-complexity peak cancellation scheme and its FPGA implementation for peak-to-average power ratio reduction

The power amplifier (PA) is the most power-hungry component in a wireless base station transmitter, and reducing the peak-to-average power ratio (PAPR) of wireless signals is an important issue for its effective use. In this paper, we focus on a field-programmable gate array (FPGA) implementation of the peak cancellation (PC) technique, which is known as the simplest method for PAPR reduction. The design issue of effective peak-cancelling pulses under the constraint on the out-of-band emission is addressed. In order to reduce its hardware complexity, a novel approach for generating peak-cancelling pulses is also presented. The experimental results based on long-term evolution (LTE)/LTE-Advanced and multi-band Wideband Code Division Multiple Access (WCDMA) signals demonstrate the validity of the proposed scheme. It has been shown that the proposed PC scheme can achieve lower in-band distortion than the conventional PC with an acceptable loss in out-of-band performance. Our study also includes mapping the signal processing methods onto a Xilinx virtex-7 FPGA device running at 245.76 MHz and addresses the resource utilization and the hardware design in detail.

Autonomous Soft-Error Tolerance of FPGA Configuration Bits

Field-programmable gate arrays (FPGAs) are increasingly susceptible to radiation-induced single event upsets (SEUs). These upsets are predominant in a space environment; however, with increasing use of static RAM (SRAM) in modern FPGAs, these SEUs are gaining prominence even in a terrestrial environment. SEUs can flip SRAM bits of FPGA, potentially altering the functionality of the implemented design. This has motivated FPGA designers to investigate techniques to protect the FPGA configuration bits against such inadvertent bit flips (soft error). Traditionally, triple modular redundancy (TMR) is used to protect the FPGA bit flips. Increasing design complexity and limited battery life motivate for alternative approaches for soft-error tolerance. In this article, we propose a technique to improve autonomous fault-masking capabilities of a design by maximizing the number of zeros or ones in lookup tables (LUTs). The technique analyzes critical configuration bits and utilizes spare resources (XOR gates and carry chains) of FPGAs to selectively manipulate the logic implemented in LUTs using two operations: LUT restructuring and LUT decomposition. We implemented the proposed approach for Xilinx Virtex-6 FPGAs and validated the same with a wide set of designs from the MCNC, IWLS 2005, and ITC99 benchmark suites. Results demonstrate that the proposed logic restructuring maximizes logic 0 (or 1) of LUTs by an average of 20%, achieving 80% fault masking with no area overhead. The fault rate of the entire design is reduced by 60% on average as compared to the existing techniques. Furthermore, the logic decomposition algorithm provides incremental fault-tolerance capabilities and achieves an additional 5% fault masking with an average 7% increase in slice usage. The complete methodology is implemented into a tool for Xilinx FPGA and is made available online for the benefit of the research community. The algorithms are lightweight, and the whole design flow (including Xilinx Place and Route) was completed in 75 minutes for the largest benchmark in the set.

The Cibola Flight Experiment

Over the past 15 years many organizations have researched the use of Static-Random Access Memory (SRAM)-based Field-Programmable Gate Arrays (FPGAs) in space. Although the components can provide a performance improvement over radiation-hardened processing components, random soft errors can occur from the naturally occurring space radiation environment. Many organizations have been developing methods for characterizing, emulating, and simulating radiation-induced events; mitigating and removing radiation-induced computational errors; and designing fault-tolerant reconfigurable spacecraft. Los Alamos National Laboratory has fielded one of the longest space-based FPGAs experiments, called the Cibola Flight Experiment (CFE), using Xilinx Virtex FPGAs. CFE has successfully deployed commercial SRAM FPGAs into a low-Earth orbit with Single-Event Upset (SEU) mitigation and was able to exploit effectively the reconfigurability and customization of FPGAs in a harsh radiation environment. Although older than current state-of-the-art FPGAs, these same concepts are used to deploy newer FPGA-based space systems since the launch of the CFE satellite and will continue to be useful for newer systems. In this article, we present how the system was designed to be fault tolerant, prelaunch predictions of expected on-orbit behaviors, and on-orbit results.

Z-TCAM: An SRAM-based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed lookup operation but when compared with static random access memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive. Thus, can we use the benefits of SRAM by configuring it (with additional logic) to enable it to behave like TCAM? This brief proposes a novel memory architecture, named Z-TCAM, which emulates the TCAM functionality with SRAM. Z-TCAM logically partitions the classical TCAM table along columns and rows into hybrid TCAM subtables, which are then processed to map on their corresponding memory blocks. Two example designs for Z-TCAM of sizes 512 × 36 and 64 × 32 have been implemented on Xilinx Virtex-7 field-programmable gate array. The design of 64 × 32 Z-TCAM has also been implemented using OSUcells library for 0.18 μm technology, which confirms the physical and technical feasibility of Z-TCAM. Search latency for each design is three clock cycles. The detailed implementation results and power measurements for each design have been reported thoroughly.

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA

Taking advantage of Three Dimension (3D) Integrated Circuit (IC) technology, 3D Network-on-Chip (NoC) is becoming a promising architecture of high-performance System-on-Chip (SoC). To model 3D NoC and to evaluate the performance fast and accurately, the simulation method is therefore critical issue. Compared to software simulation, Field Programmable Gate Array (FPGA) based simulation can offer a high speed validation process with a higher accuracy. But there still exist some difficulties such as partition, scalability and so on. This paper proposed a novel multi-FPGA simulation platform, RcEF3Ns (Reconfigurable Simulation on multi-FPGA for 3D NoCs), based on Xilinx Virtex-6 FPGAs. The design method of RcEF3Ns employs a single FPGA to manage vertical transaction independently, supporting bus and network communication mechanism. All the parameters can be dynamically reconfigured on-chip to model 3D NoC architecture without re-synthesizing. The experiments show RcEF3Ns’ speedups over 10 times without sacrificing accuracy when compared to other hardware based platform.

FPGA implementation of linear model predictive controller for real-time position control of DC motor

Model predictive control (MPC) is a predictive class of control algorithm which has been widely adopted for slow dynamic, constrained, multi-variable process control problems. The applicability of MPC for real-time control is restricted due to the associated computational complexity of quadratic programming (QP) problem and the choice of appropriate computing platforms. MPC can be formulated as a standard QP problem and according to receding horizon control strategy, in order to get optimal control signal to apply to the system, in each discrete time step, a QP problem is to be solved online. In order to meet high sampling frequency demand of real-time control applications, in this paper, we propose a novel accelerated field programmable gate array (FPGA)-based customised architecture for active set method (ASM)-based QP solver to implement linear MPC. The approach is implemented successfully on Xilinx's Virtex-4 FPGA and demonstrated practically by applying MPC to Quansers QET DC servomotor position control plant. From experimentation; it is observed that, FPGA-based implementation occupies 35% of Virtex-4 area and achieves 500 µs sample time.

Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip

Crosstalk interferences and high dynamic power consumption in a network-on-chip (NoC) are two increasingly problematic design issues. Using data codecs can reduce the switching activities on wires that cause crosstalk interferences and high dynamic power. However, data codecs have different overheads in terms of area and performance, and varying capabilities in reducing crosstalk and dynamic power. To adapt to the wide range of processing requirements incurred by applications and operating environments, a reasoning and learning (REAL) framework is proposed for a reconfigurable NoC. REAL dynamically investigates the tradeoffs among reliability, dynamic power reduction, performance, and hardware resource usages to configure the reconfigurable NoC with an appropriate data codec at runtime. As a proof of concept, a 3 × 3 reconfigurable NoC was implemented on Xilinx Virtex-4 field-programmable gate array, which required 8.2% lesser number of slices compared with a conventional NoC. Experiments show that at the same overheads of performance and hardware resources the reconfigurable NoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption.

Comparative study of system on chip based solution for floating and fixed point differential evolution algorithm

This paper presents performance study of scalable hardware accelerator for fixed and floating point differential evolution (DE) algorithms in field programmable gate array (FPGA) using programmable system on chip (PSoC) approach. The hardware intellectual property (IP) of the DE is interfaced as a Slave Unit (SU) as well as an Auxiliary Processor Unit (APU) with the PowerPC440 processor based System on Chip (SoC) platform on Xilinx Virtex-5 FPGA. Six numerical benchmark functions are optimized to validate the IP and its interface to processor. From the experimental results, it is observed that (i) Both SU and APU interfaces of fixed and float DE IPs have shown similar acceleration because of less communication overhead. (ii) Floating point DE has higher resource utilization compared to fixed point DE. (iii) Both interfaces of fixed and float DE SoC systems have shown similar power consumption. (iii) Finally as a case study, an Infinite Impulse Response (IIR) based system identification task with second and fourth order plant transfer functions is implemented on PSoC using the fixed and float DE IP cores with fabric co-processor bus (FCB) interface using APU controller. The experimental results reveal that the acceleration factor and resources utilization increases with the increase in problem complexity.

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

This brief presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM and the RAM-based LUT is found to be costly for ASIC implementation. Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly 68% and 58% less area-delay product and 78% and 59% less energy per sample than the DA-based systolic structure and the carry save adder (CSA)-based structure, respectively, for the ASIC implementation. A distributed-RAM-based design is also proposed for the field-programmable gate array (FPGA) implementation of the reconfigurable FIR filter, which supports up to 91 MHz input sampling frequency and offers 54% and 29% less the number of slices than the systolic structure and the CSA-based structure, respectively, when implemented in the Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136).

FPGA implementation of high-speed neural network for power amplifier behavioral modeling

In this paper, a high-speed pipelined architecture of dynamic neural network is proposed for power amplifier behavioral modeling. This architecture is implemented on field programmable gate array (FPGA) using Xilinx system generator and Virtex-6 FPGA ML605 Evaluation Kit. The novelty of the proposed architecture is that it provides higher operating frequency, lower output latency, and less required resources. These improvements are obtained by reducing the bit-width data and by efficiently redistributing the inserted pipelining delays. The new pipelined architecture is evaluated and compared to the conventional and pseudo-conventional ones in terms of the resource utilization, the maximum operating frequency, and the modeling performances using the 16-QAM modeled test signal. This architecture is verified using JTAG hardware co-simulation both for single step and free-running clock modes.